clk: sm1: add clk measure driver [2/2]

PD#SWPL-5407

Problem:
sm1 support clk measure

Solution:
support clk measure

Verify:
ac200

Change-Id: If87c7c0bc53c8e2bcbf58a685f9ef7ac75462a70
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>

diff --git a/drivers/amlogic/clk/clk_measure.c b/drivers/amlogic/clk/clk_measure.c
index 1ca3ef0..8473964 100644 (file)
--- a/drivers/amlogic/clk/clk_measure.c
+++ b/drivers/amlogic/clk/clk_measure.c
@@ -1492,10 +1492,148 @@ static const struct meson_clkmsr_data tl1_data = {
        .clk_msr_function = gxbb_clk_util_clk_msr,
 };
 
+static const char * const sm1_table[] = {
+       [127] = "clk_csi2_data              ",
+       [126] = "csi_phy0_clk_out           ",
+       [125] = "earcrx_pll_test_clk        ",
+       [124] = "earcx_pll_(dmac)_clk       ",
+       [123] = "audio_resampled_clk        ",
+       [122] = "mod_audio_pdm_dclk_o       ",
+       [121] = "audio_spdifin_mst_clk      ",
+       [120] = "audio_spdifout_mst_clk     ",
+       [119] = "audio_spdifout_b_mst_clk   ",
+       [118] = "audio_pdm_sysclk           ",
+       [117] = "audio_resampleA_clk         ",
+       [116] = "audio_tdmin_a_sclk         ",
+       [115] = "audio_tdmin_b_sclk         ",
+       [114] = "audio_tdmin_c_sclk         ",
+       [113] = "audio_tdmin_lb_sclk        ",
+       [112] = "audio_tdmout_a_sclk        ",
+       [111] = "audio_tdmout_b_sclk        ",
+       [110] = "audio_tdmout_c_sclk        ",
+       [109] = "c_alocker_out_clk          ",
+       [108] = "c_alocker_in_clk           ",
+       [107] = "au_dac_clk_g128x           ",
+       [106] = "ephy_test_clk              ",
+       [105] = "arm_ring_osc_clk_out[16]  ",
+       [104] = "arm_ring_osc_clk_out[15]  ",
+       [103] = "arm_ring_osc_clk_out[14]  ",
+       [102] = "arm_ring_osc_clk_out[13]  ",
+       [101] = "arm_ring_osc_clk_out[12]  ",
+       [100] = "arm_ring_osc_clk_out[11]  ",
+       [99] = "arm_ring_osc_clk_out[10]   ",
+       [98] = "cts_ts_clk                 ",
+       [97] = "cts_vpu_clkb_tmp           ",
+       [96] = "cts_vpu_clkb               ",
+       [95] = "eth_phy_plltxclk           ",
+       [94] = "eth_phy_rxclk              ",
+       [93] = "vad_clk                    ",
+       [92] = "nna_axi_clk                ",
+       [91] = "nna_core_clk               ",
+       [90] = "cts_hdmitx_sys_clk         ",
+       [89] = "HDMI_CLK_TODIG             ",
+       [88] = "csi2_adapt_clk             ",
+       [87] = "mipi_csi_phy_clk           ",
+       [86] = "arm_ring_osc_clk_out[9]    ",
+       [85] = "arm_ring_osc_clk_out[8]    ",
+       [84] = "co_tx_clk                  ",
+       [83] = "co_rx_clk                  ",
+       [82] = "cts_ge2d_clk               ",
+       [81] = "cts_vapbclk                ",
+       [80] = "rng_ring_osc_clk[3]        ",
+       [79] = "rng_ring_osc_clk[2]        ",
+       [78] = "rng_ring_osc_clk[1]        ",
+       [77] = "rng_ring_osc_clk[0]        ",
+       [76] = "arm_ring_osc_clk_out[7]    ",
+       [75] = "cts_hevcf_clk              ",
+       [74] = "arm_ring_osc_clk_out[6]    ",
+       [73] = "cts_pwm_C_clk              ",
+       [72] = "cts_pwm_D_clk              ",
+       [71] = "cts_pwm_E_clk              ",
+       [70] = "cts_pwm_F_clk              ",
+       [69] = "cts_hdcp22_skpclk          ",
+       [68] = "cts_hdcp22_esmclk          ",
+       [67] = "cts_dsi_phy_clk            ",
+       [66] = "cts_vid_lock_clk           ",
+       [65] = "cts_spicc_0_clk            ",
+       [64] = "cts_spicc_1_clk            ",
+       [63] = "cts_dsi_meas_clk           ",
+       [62] = "cts_hevcb_clk              ",
+       [61] = "gpio_clk_msr               ",
+       [60] = "arm_ring_osc_clk_out[5]    ",
+       [59] = "cts_hcodec_clk             ",
+       [58] = "cts_wave420l_bclk          ",
+       [57] = "cts_wave420l_cclk          ",
+       [56] = "cts_wave420l_aclk          ",
+       [55] = "vid_pll_div_clk_out        ",
+       [54] = "cts_vpu_clkc               ",
+       [53] = "cts_sd_emmc_clk_A          ",
+       [52] = "cts_sd_emmc_clk_B          ",
+       [51] = "cts_sd_emmc_clk_C          ",
+       [50] = "mp3_clk_out                ",
+       [49] = "mp2_clk_out                ",
+       [48] = "mp1_clk_out                ",
+       [47] = "ddr_dpll_pt_clk            ",
+       [46] = "cts_vpu_clk                ",
+       [45] = "cts_pwm_A_clk              ",
+       [44] = "cts_pwm_B_clk              ",
+       [43] = "fclk_div5                  ",
+       [42] = "mp0_clk_out                ",
+       [41] = "mac_eth_rx_clk_rmii        ",
+       [40] = "arm_ring_osc_clk_out[4]    ",
+       [39] = "cts_bt656_clk0             ",
+       [38] = "cts_vdin_meas_clk          ",
+       [37] = "cts_cdac_clk_c             ",
+       [36] = "cts_hdmi_tx_pixel_clk      ",
+       [35] = "cts_mali_clk               ",
+       [34] = "eth_mppll_50m_ckout        ",
+       [33] = "1'b0                       ",
+       [32] = "cts_vdec_clk               ",
+       [31] = "mpll_clk_test_out          ",
+       [30] = "pcie_clk_inn               ",
+       [29] = "pcie_clk_inp               ",
+       [28] = "cts_sar_adc_clk            ",
+       [27] = "co_clkin_to_mac            ",
+       [26] = "sc_clk_int                 ",
+       [25] = "cts_eth_clk_rmii           ",
+       [24] = "cts_eth_clk125Mhz          ",
+       [23] = "mpll_clk_50m               ",
+       [22] = "mac_eth_phy_ref_clk        ",
+       [21] = "lcd_an_clk_ph3             ",
+       [20] = "rtc_osc_clk_out            ",
+       [19] = "lcd_an_clk_ph2             ",
+       [18] = "sys_cpu_clk_div16          ",
+       [17] = "sys_pll_div16              ",
+       [16] = "cts_FEC_CLK_2              ",
+       [15] = "cts_FEC_CLK_1              ",
+       [14] = "cts_FEC_CLK_0              ",
+       [13] = "mod_tcon_clko              ",
+       [12] = "hifi_pll_clk               ",
+       [11] = "mac_eth_tx_clk             ",
+       [10] = "cts_vdac_clk               ",
+       [9] = "cts_encl_clk             ",
+       [8] = "cts_encp_clk             ",
+       [7] = "clk81                    ",
+       [6] = "cts_enci_clk             ",
+       [5] = "gp1_pll_clk              ",
+       [4] = "gp0_pll_clk              ",
+       [3] = "am_ring_osc_clk_out_ee[3]",
+       [2] = "am_ring_osc_clk_out_ee[2]",
+       [1] = "am_ring_osc_clk_out_ee[1]",
+       [0] = "am_ring_osc_clk_out_ee[0]",
+};
+
+static const struct meson_clkmsr_data sm1_data = {
+       .clk_table = sm1_table,
+       .table_size = ARRAY_SIZE(sm1_table),
+       .clk_msr_function = gxbb_clk_util_clk_msr,
+};
+
 static const struct of_device_id meson_clkmsr_dt_match[] = {
        {       .compatible = "amlogic, gxl_measure",},
        {       .compatible = "amlogic, m8b_measure",},
        {       .compatible = "amlogic,tl1-measure", .data = &tl1_data },
+       {       .compatible = "amlogic, sm1-measure", .data = &sm1_data },
 
        {},
 };