* Keith Whitwell <keith@tungstengraphics.com>
*/
-#ifndef BRW_DEFINES_H
-#define BRW_DEFINES_H
+#ifndef GEN_DEFINES_H
+#define GEN_DEFINES_H
#include <cstdint>
#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
/* Execution Unit (EU) defines */
-#define BRW_ALIGN_1 0
-#define BRW_ALIGN_16 1
+#define GEN_ALIGN_1 0
+#define GEN_ALIGN_16 1
-#define BRW_ADDRESS_DIRECT 0
-#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
+#define GEN_ADDRESS_DIRECT 0
+#define GEN_ADDRESS_REGISTER_INDIRECT_REGISTER 1
-#define BRW_CHANNEL_X 0
-#define BRW_CHANNEL_Y 1
-#define BRW_CHANNEL_Z 2
-#define BRW_CHANNEL_W 3
+#define GEN_CHANNEL_X 0
+#define GEN_CHANNEL_Y 1
+#define GEN_CHANNEL_Z 2
+#define GEN_CHANNEL_W 3
enum brw_compression {
- BRW_COMPRESSION_NONE = 0,
- BRW_COMPRESSION_2NDHALF = 1,
- BRW_COMPRESSION_COMPRESSED = 2,
+ GEN_COMPRESSION_NONE = 0,
+ GEN_COMPRESSION_2NDHALF = 1,
+ GEN_COMPRESSION_COMPRESSED = 2,
};
#define GEN6_COMPRESSION_1Q 0
#define GEN6_COMPRESSION_1H 0
#define GEN6_COMPRESSION_2H 2
-#define BRW_CONDITIONAL_NONE 0
-#define BRW_CONDITIONAL_Z 1
-#define BRW_CONDITIONAL_NZ 2
-#define BRW_CONDITIONAL_EQ 1 /* Z */
-#define BRW_CONDITIONAL_NEQ 2 /* NZ */
-#define BRW_CONDITIONAL_G 3
-#define BRW_CONDITIONAL_GE 4
-#define BRW_CONDITIONAL_L 5
-#define BRW_CONDITIONAL_LE 6
-#define BRW_CONDITIONAL_R 7
-#define BRW_CONDITIONAL_O 8
-#define BRW_CONDITIONAL_U 9
-
-#define BRW_DEBUG_NONE 0
-#define BRW_DEBUG_BREAKPOINT 1
-
-#define BRW_DEPENDENCY_NORMAL 0
-#define BRW_DEPENDENCY_NOTCLEARED 1
-#define BRW_DEPENDENCY_NOTCHECKED 2
-#define BRW_DEPENDENCY_DISABLE 3
-
-#define BRW_EXECUTE_1 0
-#define BRW_EXECUTE_2 1
-#define BRW_EXECUTE_4 2
-#define BRW_EXECUTE_8 3
-#define BRW_EXECUTE_16 4
-#define BRW_EXECUTE_32 5
-
-#define BRW_HORIZONTAL_STRIDE_0 0
-#define BRW_HORIZONTAL_STRIDE_1 1
-#define BRW_HORIZONTAL_STRIDE_2 2
-#define BRW_HORIZONTAL_STRIDE_4 3
-
-#define BRW_INSTRUCTION_NORMAL 0
-#define BRW_INSTRUCTION_SATURATE 1
-
-#define BRW_MASK_ENABLE 0
-#define BRW_MASK_DISABLE 1
+#define GEN_CONDITIONAL_NONE 0
+#define GEN_CONDITIONAL_Z 1
+#define GEN_CONDITIONAL_NZ 2
+#define GEN_CONDITIONAL_EQ 1 /* Z */
+#define GEN_CONDITIONAL_NEQ 2 /* NZ */
+#define GEN_CONDITIONAL_G 3
+#define GEN_CONDITIONAL_GE 4
+#define GEN_CONDITIONAL_L 5
+#define GEN_CONDITIONAL_LE 6
+#define GEN_CONDITIONAL_R 7
+#define GEN_CONDITIONAL_O 8
+#define GEN_CONDITIONAL_U 9
+
+#define GEN_DEBUG_NONE 0
+#define GEN_DEBUG_BREAKPOINT 1
+
+#define GEN_DEPENDENCY_NORMAL 0
+#define GEN_DEPENDENCY_NOTCLEARED 1
+#define GEN_DEPENDENCY_NOTCHECKED 2
+#define GEN_DEPENDENCY_DISABLE 3
+
+#define GEN_EXECUTE_1 0
+#define GEN_EXECUTE_2 1
+#define GEN_EXECUTE_4 2
+#define GEN_EXECUTE_8 3
+#define GEN_EXECUTE_16 4
+#define GEN_EXECUTE_32 5
+
+#define GEN_HORIZONTAL_STRIDE_0 0
+#define GEN_HORIZONTAL_STRIDE_1 1
+#define GEN_HORIZONTAL_STRIDE_2 2
+#define GEN_HORIZONTAL_STRIDE_4 3
+
+#define GEN_INSTRUCTION_NORMAL 0
+#define GEN_INSTRUCTION_SATURATE 1
+
+#define GEN_MASK_ENABLE 0
+#define GEN_MASK_DISABLE 1
/** @{
*
* This is the default value. It means that a channel's write enable is set
* if the per-channel IP is pointing at this instruction.
*/
-#define BRW_WE_NORMAL 0
+#define GEN_WE_NORMAL 0
/**
- * This is used like BRW_MASK_DISABLE, and causes all channels to have
+ * This is used like GEN_MASK_DISABLE, and causes all channels to have
* their write enable set. Note that predication still contributes to
* whether the channel actually gets written.
*/
-#define BRW_WE_ALL 1
+#define GEN_WE_ALL 1
/** @} */
enum opcode {
/* These are the actual hardware opcodes. */
- BRW_OPCODE_MOV = 1,
- BRW_OPCODE_SEL = 2,
- BRW_OPCODE_NOT = 4,
- BRW_OPCODE_AND = 5,
- BRW_OPCODE_OR = 6,
- BRW_OPCODE_XOR = 7,
- BRW_OPCODE_SHR = 8,
- BRW_OPCODE_SHL = 9,
- BRW_OPCODE_RSR = 10,
- BRW_OPCODE_RSL = 11,
- BRW_OPCODE_ASR = 12,
- BRW_OPCODE_CMP = 16,
- BRW_OPCODE_CMPN = 17,
- BRW_OPCODE_JMPI = 32,
- BRW_OPCODE_IF = 34,
- BRW_OPCODE_IFF = 35,
- BRW_OPCODE_ELSE = 36,
- BRW_OPCODE_ENDIF = 37,
- BRW_OPCODE_DO = 38,
- BRW_OPCODE_WHILE = 39,
- BRW_OPCODE_BREAK = 40,
- BRW_OPCODE_CONTINUE = 41,
- BRW_OPCODE_HALT = 42,
- BRW_OPCODE_MSAVE = 44,
- BRW_OPCODE_MRESTORE = 45,
- BRW_OPCODE_PUSH = 46,
- BRW_OPCODE_POP = 47,
- BRW_OPCODE_WAIT = 48,
- BRW_OPCODE_SEND = 49,
- BRW_OPCODE_SENDC = 50,
- BRW_OPCODE_MATH = 56,
- BRW_OPCODE_ADD = 64,
- BRW_OPCODE_MUL = 65,
- BRW_OPCODE_AVG = 66,
- BRW_OPCODE_FRC = 67,
- BRW_OPCODE_RNDU = 68,
- BRW_OPCODE_RNDD = 69,
- BRW_OPCODE_RNDE = 70,
- BRW_OPCODE_RNDZ = 71,
- BRW_OPCODE_MAC = 72,
- BRW_OPCODE_MACH = 73,
- BRW_OPCODE_LZD = 74,
- BRW_OPCODE_SAD2 = 80,
- BRW_OPCODE_SADA2 = 81,
- BRW_OPCODE_DP4 = 84,
- BRW_OPCODE_DPH = 85,
- BRW_OPCODE_DP3 = 86,
- BRW_OPCODE_DP2 = 87,
- BRW_OPCODE_DPA2 = 88,
- BRW_OPCODE_LINE = 89,
- BRW_OPCODE_PLN = 90,
- BRW_OPCODE_MAD = 91,
- BRW_OPCODE_NOP = 126,
+ GEN_OPCODE_MOV = 1,
+ GEN_OPCODE_SEL = 2,
+ GEN_OPCODE_NOT = 4,
+ GEN_OPCODE_AND = 5,
+ GEN_OPCODE_OR = 6,
+ GEN_OPCODE_XOR = 7,
+ GEN_OPCODE_SHR = 8,
+ GEN_OPCODE_SHL = 9,
+ GEN_OPCODE_RSR = 10,
+ GEN_OPCODE_RSL = 11,
+ GEN_OPCODE_ASR = 12,
+ GEN_OPCODE_CMP = 16,
+ GEN_OPCODE_CMPN = 17,
+ GEN_OPCODE_JMPI = 32,
+ GEN_OPCODE_IF = 34,
+ GEN_OPCODE_IFF = 35,
+ GEN_OPCODE_ELSE = 36,
+ GEN_OPCODE_ENDIF = 37,
+ GEN_OPCODE_DO = 38,
+ GEN_OPCODE_WHILE = 39,
+ GEN_OPCODE_BREAK = 40,
+ GEN_OPCODE_CONTINUE = 41,
+ GEN_OPCODE_HALT = 42,
+ GEN_OPCODE_MSAVE = 44,
+ GEN_OPCODE_MRESTORE = 45,
+ GEN_OPCODE_PUSH = 46,
+ GEN_OPCODE_POP = 47,
+ GEN_OPCODE_WAIT = 48,
+ GEN_OPCODE_SEND = 49,
+ GEN_OPCODE_SENDC = 50,
+ GEN_OPCODE_MATH = 56,
+ GEN_OPCODE_ADD = 64,
+ GEN_OPCODE_MUL = 65,
+ GEN_OPCODE_AVG = 66,
+ GEN_OPCODE_FRC = 67,
+ GEN_OPCODE_RNDU = 68,
+ GEN_OPCODE_RNDD = 69,
+ GEN_OPCODE_RNDE = 70,
+ GEN_OPCODE_RNDZ = 71,
+ GEN_OPCODE_MAC = 72,
+ GEN_OPCODE_MACH = 73,
+ GEN_OPCODE_LZD = 74,
+ GEN_OPCODE_SAD2 = 80,
+ GEN_OPCODE_SADA2 = 81,
+ GEN_OPCODE_DP4 = 84,
+ GEN_OPCODE_DPH = 85,
+ GEN_OPCODE_DP3 = 86,
+ GEN_OPCODE_DP2 = 87,
+ GEN_OPCODE_DPA2 = 88,
+ GEN_OPCODE_LINE = 89,
+ GEN_OPCODE_PLN = 90,
+ GEN_OPCODE_MAD = 91,
+ GEN_OPCODE_NOP = 126,
/* These are compiler backend opcodes that get translated into other
* instructions.
VS_OPCODE_PULL_CONSTANT_LOAD,
};
-#define BRW_PREDICATE_NONE 0
-#define BRW_PREDICATE_NORMAL 1
-#define BRW_PREDICATE_ALIGN1_ANYV 2
-#define BRW_PREDICATE_ALIGN1_ALLV 3
-#define BRW_PREDICATE_ALIGN1_ANY2H 4
-#define BRW_PREDICATE_ALIGN1_ALL2H 5
-#define BRW_PREDICATE_ALIGN1_ANY4H 6
-#define BRW_PREDICATE_ALIGN1_ALL4H 7
-#define BRW_PREDICATE_ALIGN1_ANY8H 8
-#define BRW_PREDICATE_ALIGN1_ALL8H 9
-#define BRW_PREDICATE_ALIGN1_ANY16H 10
-#define BRW_PREDICATE_ALIGN1_ALL16H 11
-#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2
-#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3
-#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4
-#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5
-#define BRW_PREDICATE_ALIGN16_ANY4H 6
-#define BRW_PREDICATE_ALIGN16_ALL4H 7
-
-#define BRW_ARCHITECTURE_REGISTER_FILE 0
-#define BRW_GENERAL_REGISTER_FILE 1
-#define BRW_IMMEDIATE_VALUE 3
-
-#define BRW_REGISTER_TYPE_UD 0
-#define BRW_REGISTER_TYPE_D 1
-#define BRW_REGISTER_TYPE_UW 2
-#define BRW_REGISTER_TYPE_W 3
-#define BRW_REGISTER_TYPE_UB 4
-#define BRW_REGISTER_TYPE_B 5
-#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */
-#define BRW_REGISTER_TYPE_HF 6
-#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */
-#define BRW_REGISTER_TYPE_F 7
-
-#define BRW_ARF_NULL 0x00
-#define BRW_ARF_ADDRESS 0x10
-#define BRW_ARF_ACCUMULATOR 0x20
-#define BRW_ARF_FLAG 0x30
-#define BRW_ARF_MASK 0x40
-#define BRW_ARF_MASK_STACK 0x50
-#define BRW_ARF_MASK_STACK_DEPTH 0x60
-#define BRW_ARF_STATE 0x70
-#define BRW_ARF_CONTROL 0x80
-#define BRW_ARF_NOTIFICATION_COUNT 0x90
-#define BRW_ARF_IP 0xA0
-
-#define BRW_MRF_COMPR4 (1 << 7)
-
-#define BRW_AMASK 0
-#define BRW_IMASK 1
-#define BRW_LMASK 2
-#define BRW_CMASK 3
-
-
-
-#define BRW_THREAD_NORMAL 0
-#define BRW_THREAD_ATOMIC 1
-#define BRW_THREAD_SWITCH 2
-
-#define BRW_VERTICAL_STRIDE_0 0
-#define BRW_VERTICAL_STRIDE_1 1
-#define BRW_VERTICAL_STRIDE_2 2
-#define BRW_VERTICAL_STRIDE_4 3
-#define BRW_VERTICAL_STRIDE_8 4
-#define BRW_VERTICAL_STRIDE_16 5
-#define BRW_VERTICAL_STRIDE_32 6
-#define BRW_VERTICAL_STRIDE_64 7
-#define BRW_VERTICAL_STRIDE_128 8
-#define BRW_VERTICAL_STRIDE_256 9
-#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
-
-#define BRW_WIDTH_1 0
-#define BRW_WIDTH_2 1
-#define BRW_WIDTH_4 2
-#define BRW_WIDTH_8 3
-#define BRW_WIDTH_16 4
-
-#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0
-#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1
-#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2
-#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3
-#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4
-#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5
-#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6
-#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7
-#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8
-#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9
-#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10
-#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11
-
-#define BRW_POLYGON_FACING_FRONT 0
-#define BRW_POLYGON_FACING_BACK 1
+#define GEN_PREDICATE_NONE 0
+#define GEN_PREDICATE_NORMAL 1
+#define GEN_PREDICATE_ALIGN1_ANYV 2
+#define GEN_PREDICATE_ALIGN1_ALLV 3
+#define GEN_PREDICATE_ALIGN1_ANY2H 4
+#define GEN_PREDICATE_ALIGN1_ALL2H 5
+#define GEN_PREDICATE_ALIGN1_ANY4H 6
+#define GEN_PREDICATE_ALIGN1_ALL4H 7
+#define GEN_PREDICATE_ALIGN1_ANY8H 8
+#define GEN_PREDICATE_ALIGN1_ALL8H 9
+#define GEN_PREDICATE_ALIGN1_ANY16H 10
+#define GEN_PREDICATE_ALIGN1_ALL16H 11
+#define GEN_PREDICATE_ALIGN16_REPLICATE_X 2
+#define GEN_PREDICATE_ALIGN16_REPLICATE_Y 3
+#define GEN_PREDICATE_ALIGN16_REPLICATE_Z 4
+#define GEN_PREDICATE_ALIGN16_REPLICATE_W 5
+#define GEN_PREDICATE_ALIGN16_ANY4H 6
+#define GEN_PREDICATE_ALIGN16_ALL4H 7
+
+#define GEN_ARCHITECTURE_REGISTER_FILE 0
+#define GEN_GENERAL_REGISTER_FILE 1
+#define GEN_IMMEDIATE_VALUE 3
+
+#define GEN_REGISTER_TYPE_UD 0
+#define GEN_REGISTER_TYPE_D 1
+#define GEN_REGISTER_TYPE_UW 2
+#define GEN_REGISTER_TYPE_W 3
+#define GEN_REGISTER_TYPE_UB 4
+#define GEN_REGISTER_TYPE_B 5
+#define GEN_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */
+#define GEN_REGISTER_TYPE_HF 6
+#define GEN_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */
+#define GEN_REGISTER_TYPE_F 7
+
+#define GEN_ARF_NULL 0x00
+#define GEN_ARF_ADDRESS 0x10
+#define GEN_ARF_ACCUMULATOR 0x20
+#define GEN_ARF_FLAG 0x30
+#define GEN_ARF_MASK 0x40
+#define GEN_ARF_MASK_STACK 0x50
+#define GEN_ARF_MASK_STACK_DEPTH 0x60
+#define GEN_ARF_STATE 0x70
+#define GEN_ARF_CONTROL 0x80
+#define GEN_ARF_NOTIFICATION_COUNT 0x90
+#define GEN_ARF_IP 0xA0
+
+#define GEN_MRF_COMPR4 (1 << 7)
+
+#define GEN_AMASK 0
+#define GEN_IMASK 1
+#define GEN_LMASK 2
+#define GEN_CMASK 3
+
+
+
+#define GEN_THREAD_NORMAL 0
+#define GEN_THREAD_ATOMIC 1
+#define GEN_THREAD_SWITCH 2
+
+#define GEN_VERTICAL_STRIDE_0 0
+#define GEN_VERTICAL_STRIDE_1 1
+#define GEN_VERTICAL_STRIDE_2 2
+#define GEN_VERTICAL_STRIDE_4 3
+#define GEN_VERTICAL_STRIDE_8 4
+#define GEN_VERTICAL_STRIDE_16 5
+#define GEN_VERTICAL_STRIDE_32 6
+#define GEN_VERTICAL_STRIDE_64 7
+#define GEN_VERTICAL_STRIDE_128 8
+#define GEN_VERTICAL_STRIDE_256 9
+#define GEN_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
+
+#define GEN_WIDTH_1 0
+#define GEN_WIDTH_2 1
+#define GEN_WIDTH_4 2
+#define GEN_WIDTH_8 3
+#define GEN_WIDTH_16 4
+
+#define GEN_STATELESS_BUFFER_BOUNDARY_1K 0
+#define GEN_STATELESS_BUFFER_BOUNDARY_2K 1
+#define GEN_STATELESS_BUFFER_BOUNDARY_4K 2
+#define GEN_STATELESS_BUFFER_BOUNDARY_8K 3
+#define GEN_STATELESS_BUFFER_BOUNDARY_16K 4
+#define GEN_STATELESS_BUFFER_BOUNDARY_32K 5
+#define GEN_STATELESS_BUFFER_BOUNDARY_64K 6
+#define GEN_STATELESS_BUFFER_BOUNDARY_128K 7
+#define GEN_STATELESS_BUFFER_BOUNDARY_256K 8
+#define GEN_STATELESS_BUFFER_BOUNDARY_512K 9
+#define GEN_STATELESS_BUFFER_BOUNDARY_1M 10
+#define GEN_STATELESS_BUFFER_BOUNDARY_2M 11
+
+#define GEN_POLYGON_FACING_FRONT 0
+#define GEN_POLYGON_FACING_BACK 1
/**
* Message target: Shared Function ID for where to SEND a message.
* Overview / GPE Function IDs
*/
enum brw_message_target {
- BRW_SFID_NULL = 0,
- BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
- BRW_SFID_SAMPLER = 2,
- BRW_SFID_MESSAGE_GATEWAY = 3,
- BRW_SFID_DATAPORT_READ = 4,
- BRW_SFID_DATAPORT_WRITE = 5,
- BRW_SFID_URB = 6,
- BRW_SFID_THREAD_SPAWNER = 7,
+ GEN_SFID_NULL = 0,
+ GEN_SFID_MATH = 1, /* Only valid on Gen4-5 */
+ GEN_SFID_SAMPLER = 2,
+ GEN_SFID_MESSAGE_GATEWAY = 3,
+ GEN_SFID_DATAPORT_READ = 4,
+ GEN_SFID_DATAPORT_WRITE = 5,
+ GEN_SFID_URB = 6,
+ GEN_SFID_THREAD_SPAWNER = 7,
GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
-#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
-#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
-#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
-
-#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
-#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
-#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
-#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
-#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
-#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
-#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
-#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
-#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
-#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
-#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
-#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
-#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
-#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
-#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
-#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
-#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
-#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
+#define GEN_SAMPLER_RETURN_FORMAT_FLOAT32 0
+#define GEN_SAMPLER_RETURN_FORMAT_UINT32 2
+#define GEN_SAMPLER_RETURN_FORMAT_SINT32 3
+
+#define GEN_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
+#define GEN_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
+#define GEN_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
+#define GEN_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
+#define GEN_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
+#define GEN_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
+#define GEN_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
+#define GEN_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
+#define GEN_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
+#define GEN_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
+#define GEN_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
+#define GEN_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
+#define GEN_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
+#define GEN_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
+#define GEN_SAMPLER_MESSAGE_SIMD16_RESINFO 2
+#define GEN_SAMPLER_MESSAGE_SIMD4X2_LD 3
+#define GEN_SAMPLER_MESSAGE_SIMD8_LD 3
+#define GEN_SAMPLER_MESSAGE_SIMD16_LD 3
#define GEN5_SAMPLER_MESSAGE_SAMPLE 0
#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
#define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
/* for GEN5 only */
-#define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
-#define BRW_SAMPLER_SIMD_MODE_SIMD8 1
-#define BRW_SAMPLER_SIMD_MODE_SIMD16 2
-#define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
+#define GEN_SAMPLER_SIMD_MODE_SIMD4X2 0
+#define GEN_SAMPLER_SIMD_MODE_SIMD8 1
+#define GEN_SAMPLER_SIMD_MODE_SIMD16 2
+#define GEN_SAMPLER_SIMD_MODE_SIMD32_64 3
-#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
-#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
-#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
-#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
-#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
+#define GEN_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
+#define GEN_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
+#define GEN_DATAPORT_OWORD_BLOCK_2_OWORDS 2
+#define GEN_DATAPORT_OWORD_BLOCK_4_OWORDS 3
+#define GEN_DATAPORT_OWORD_BLOCK_8_OWORDS 4
-#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
-#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
+#define GEN_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
+#define GEN_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
-#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
-#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
+#define GEN_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
+#define GEN_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
/* This one stays the same across generations. */
-#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
+#define GEN_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
/* GEN4 */
-#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
-#define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
-#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
+#define GEN_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
+#define GEN_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
+#define GEN_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
/* G45, GEN5 */
#define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
#define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
#define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
-#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
-#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
-#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
+#define GEN_DATAPORT_READ_TARGET_DATA_CACHE 0
+#define GEN_DATAPORT_READ_TARGET_RENDER_CACHE 1
+#define GEN_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
-#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
-#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
-#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
-#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
-#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
+#define GEN_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
+#define GEN_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
+#define GEN_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
+#define GEN_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
+#define GEN_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
-#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
-#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
-#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
-#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
-#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
-#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
-#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
+#define GEN_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
+#define GEN_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
+#define GEN_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
+#define GEN_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
+#define GEN_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
+#define GEN_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
+#define GEN_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
/* GEN6 */
#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
/* GEN7 */
#define GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 10
-#define BRW_MATH_FUNCTION_INV 1
-#define BRW_MATH_FUNCTION_LOG 2
-#define BRW_MATH_FUNCTION_EXP 3
-#define BRW_MATH_FUNCTION_SQRT 4
-#define BRW_MATH_FUNCTION_RSQ 5
-#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */
-#define BRW_MATH_FUNCTION_COS 7 /* was 8 */
-#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */
-#define BRW_MATH_FUNCTION_TAN 9 /* gen4 */
-#define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
-#define BRW_MATH_FUNCTION_POW 10
-#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
-#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
-#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
+#define GEN_MATH_FUNCTION_INV 1
+#define GEN_MATH_FUNCTION_LOG 2
+#define GEN_MATH_FUNCTION_EXP 3
+#define GEN_MATH_FUNCTION_SQRT 4
+#define GEN_MATH_FUNCTION_RSQ 5
+#define GEN_MATH_FUNCTION_SIN 6 /* was 7 */
+#define GEN_MATH_FUNCTION_COS 7 /* was 8 */
+#define GEN_MATH_FUNCTION_SINCOS 8 /* was 6 */
+#define GEN_MATH_FUNCTION_TAN 9 /* gen4 */
+#define GEN_MATH_FUNCTION_FDIV 9 /* gen6+ */
+#define GEN_MATH_FUNCTION_POW 10
+#define GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
+#define GEN_MATH_FUNCTION_INT_DIV_QUOTIENT 12
+#define GEN_MATH_FUNCTION_INT_DIV_REMAINDER 13
-#define BRW_MATH_INTEGER_UNSIGNED 0
-#define BRW_MATH_INTEGER_SIGNED 1
+#define GEN_MATH_INTEGER_UNSIGNED 0
+#define GEN_MATH_INTEGER_SIGNED 1
-#define BRW_MATH_PRECISION_FULL 0
-#define BRW_MATH_PRECISION_PARTIAL 1
+#define GEN_MATH_PRECISION_FULL 0
+#define GEN_MATH_PRECISION_PARTIAL 1
-#define BRW_MATH_SATURATE_NONE 0
-#define BRW_MATH_SATURATE_SATURATE 1
+#define GEN_MATH_SATURATE_NONE 0
+#define GEN_MATH_SATURATE_SATURATE 1
-#define BRW_MATH_DATA_VECTOR 0
-#define BRW_MATH_DATA_SCALAR 1
+#define GEN_MATH_DATA_VECTOR 0
+#define GEN_MATH_DATA_SCALAR 1
-#define BRW_URB_OPCODE_WRITE 0
+#define GEN_URB_OPCODE_WRITE 0
-#define BRW_URB_SWIZZLE_NONE 0
-#define BRW_URB_SWIZZLE_INTERLEAVE 1
-#define BRW_URB_SWIZZLE_TRANSPOSE 2
+#define GEN_URB_SWIZZLE_NONE 0
+#define GEN_URB_SWIZZLE_INTERLEAVE 1
+#define GEN_URB_SWIZZLE_TRANSPOSE 2
#define CMD_URB_FENCE 0x6000
#define CMD_CS_URB_STATE 0x6001
# define GEN6_VS_CACHE_DISABLE (1 << 1)
# define GEN6_VS_ENABLE (1 << 0)
-#define BRW_DEREFERENCE_URB 0
-#define BRW_DO_NOT_DEREFERENCE_URB 1
+#define GEN_DEREFERENCE_URB 0
+#define GEN_DO_NOT_DEREFERENCE_URB 1
/* Maximum number of entries that can be addressed using a binding table
* pointer of type SURFTYPE_BUFFER
*/
-#define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27)
+#define GEN_MAX_NUM_BUFFER_ENTRIES (1 << 27)
/////////////////////////////////////////////////////////////////////////////
// Gen EU structures
/////////////////////////////////////////////////////////////////////////////
/** Number of general purpose registers (VS, WM, etc) */
-#define BRW_MAX_GRF 128
+#define GEN_MAX_GRF 128
/**
* First GRF used for the MRF hack.
#define GEN7_MRF_HACK_START 112.
/** Number of message register file registers */
-#define BRW_MAX_MRF 16
+#define GEN_MAX_MRF 16
struct brw_urb_immediate {
uint32_t opcode:4;
};
/* Instruction format for the execution units */
-struct brw_instruction
+struct GenInstruction
{
struct
{
} bits3;
};
-#endif /* BRW_DEFINES_H */
+#endif /* GEN_DEFINES_H */
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
-#ifndef BRW_EU_H
-#define BRW_EU_H
+#ifndef GEN_EU_H
+#define GEN_EU_H
-#include <stdbool.h>
-#include <assert.h>
-#include "brw_structs.h"
-#include "brw_defines.h"
+#include "backend/gen/brw_defines.h"
+#include "sys/platform.hpp"
+#include <cassert>
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
+#define GEN_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
+#define GEN_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
-#define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
-#define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
-
-#define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
-#define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
-#define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
-#define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
-#define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
-#define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
-#define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
+#define GEN_SWIZZLE_NOOP GEN_SWIZZLE4(0,1,2,3)
+#define GEN_SWIZZLE_XYZW GEN_SWIZZLE4(0,1,2,3)
+#define GEN_SWIZZLE_XXXX GEN_SWIZZLE4(0,0,0,0)
+#define GEN_SWIZZLE_YYYY GEN_SWIZZLE4(1,1,1,1)
+#define GEN_SWIZZLE_ZZZZ GEN_SWIZZLE4(2,2,2,2)
+#define GEN_SWIZZLE_WWWW GEN_SWIZZLE4(3,3,3,3)
+#define GEN_SWIZZLE_XYXY GEN_SWIZZLE4(0,1,0,1)
#define WRITEMASK_X 0x1
#define WRITEMASK_Y 0x2
#define WRITEMASK_YZW 0xe
#define WRITEMASK_XYZW 0xf
-static inline bool brw_is_single_value_swizzle(int swiz)
+static INLINE bool brw_is_single_value_swizzle(int swiz)
{
- return (swiz == BRW_SWIZZLE_XXXX ||
- swiz == BRW_SWIZZLE_YYYY ||
- swiz == BRW_SWIZZLE_ZZZZ ||
- swiz == BRW_SWIZZLE_WWWW);
+ return (swiz == GEN_SWIZZLE_XXXX ||
+ swiz == GEN_SWIZZLE_YYYY ||
+ swiz == GEN_SWIZZLE_ZZZZ ||
+ swiz == GEN_SWIZZLE_WWWW);
}
#define REG_SIZE (8*4)
* WM programs to implement shaders decomposed into "channel serial"
* or "structure of array" form:
*/
-struct brw_reg
+struct GenReg
{
uint32_t type:4;
uint32_t file:2;
} dw1;
};
-struct brw_indirect {
+struct GenIndirect {
uint32_t addr_subnr:4;
int addr_offset:10;
uint32_t pad:18;
};
-#define BRW_EU_MAX_INSN_STACK 5
-#define BRW_MAX_INSTRUCTION_NUM 8192
-struct brw_compile {
+#define GEN_EU_MAX_INSN_STACK 5
+#define GEN_MAX_INSTRUCTION_NUM 8192
+struct GenEmitter {
int gen;
- brw_instruction store[8192];
+ GenInstruction store[8192];
int store_size;
uint32_t nr_insn;
/* Allow clients to push/pop instruction state */
- brw_instruction stack[BRW_EU_MAX_INSN_STACK];
- bool compressed_stack[BRW_EU_MAX_INSN_STACK];
+ GenInstruction stack[GEN_EU_MAX_INSN_STACK];
+ bool compressed_stack[GEN_EU_MAX_INSN_STACK];
uint32_t flag_value;
bool single_program_flow;
bool compressed;
- struct brw_context *brw;
- inline brw_instruction *current_insn(void) { return &this->store[this->nr_insn]; }
+ INLINE GenInstruction *current_insn(void) { return &this->store[this->nr_insn]; }
- void guess_execution_size(brw_instruction *insn, brw_reg reg);
- void brw_set_mask_control(uint32_t value);
- void brw_set_saturate(uint32_t value);
- void brw_set_access_mode(uint32_t access_mode);
- void brw_set_compression_control(enum brw_compression c);
- void brw_set_predicate_control_flag_value(uint32_t value);
- void brw_set_predicate_control(uint32_t pc);
- void brw_set_predicate_inverse(bool predicate_inverse);
- void brw_set_conditionalmod(uint32_t conditional);
- void brw_set_acc_write_control(uint32_t value);
+ void guess_execution_size(GenInstruction *insn, GenReg reg);
+ void set_mask_control(uint32_t value);
+ void set_saturate(uint32_t value);
+ void set_access_mode(uint32_t access_mode);
+ void set_compression_control(enum brw_compression c);
+ void set_predicate_control_flag_value(uint32_t value);
+ void set_predicate_control(uint32_t pc);
+ void set_predicate_inverse(bool predicate_inverse);
+ void set_conditionalmod(uint32_t conditional);
+ void set_acc_write_control(uint32_t value);
- void brw_init_compile(struct brw_context *, void *mem_ctx);
- const uint32_t *brw_get_program(uint32_t *sz);
+ void init_compile(struct context *, void *mem_ctx);
+ const uint32_t *get_program(uint32_t *sz);
- brw_instruction *brw_next_insn(uint32_t opcode);
- void brw_set_dest(brw_instruction *insn, brw_reg dest);
- void brw_set_src0(brw_instruction *insn, brw_reg reg);
- void gen6_resolve_implied_move(brw_reg *src, uint32_t msg_reg_nr);
+ GenInstruction *next_insn(uint32_t opcode);
+ void set_dest(GenInstruction *insn, GenReg dest);
+ void set_src0(GenInstruction *insn, GenReg reg);
+ void gen6_resolve_implied_move(GenReg *src, uint32_t msg_reg_nr);
-#define ALU1(OP) \
- brw_instruction *brw_##OP(brw_reg dest, brw_reg src0);
+#define ALU1(OP) \
+ GenInstruction *OP(GenReg dest, GenReg src0);
-#define ALU2(OP) \
- brw_instruction *brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1);
+#define ALU2(OP) \
+ GenInstruction *OP(GenReg dest, GenReg src0, GenReg src1);
-#define ALU3(OP) \
- brw_instruction *brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1, brw_reg src2);
+#define ALU3(OP) \
+ GenInstruction *OP(GenReg dest, GenReg src0, GenReg src1, GenReg src2);
#define ROUND(OP) \
- void brw_##OP(brw_reg dest, brw_reg src0);
+ void OP(GenReg dest, GenReg src0);
ALU1(MOV)
ALU2(SEL)
#undef ROUND
/* Helpers for SEND instruction */
- void brw_set_sampler_message(brw_instruction *insn,
+ void set_sampler_message(GenInstruction *insn,
uint32_t binding_table_index,
uint32_t sampler,
uint32_t msg_type,
uint32_t simd_mode,
uint32_t return_format);
- void brw_set_dp_read_message(brw_instruction *insn,
+ void set_dp_read_message(GenInstruction *insn,
uint32_t binding_table_index,
uint32_t msg_control,
uint32_t msg_type,
uint32_t msg_length,
uint32_t response_length);
- void brw_set_dp_write_message(brw_instruction *insn,
+ void set_dp_write_message(GenInstruction *insn,
uint32_t binding_table_index,
uint32_t msg_control,
uint32_t msg_type,
uint32_t end_of_thread,
uint32_t send_commit_msg);
- void brw_SAMPLE(brw_reg dest,
+ void SAMPLE(GenReg dest,
uint32_t msg_reg_nr,
- brw_reg src0,
+ GenReg src0,
uint32_t binding_table_index,
uint32_t sampler,
uint32_t writemask,
uint32_t simd_mode,
uint32_t return_format);
- void brw_math_16(brw_reg dest,
+ void math_16(GenReg dest,
uint32_t function,
uint32_t saturate,
uint32_t msg_reg_nr,
- brw_reg src,
+ GenReg src,
uint32_t precision);
- void brw_math(brw_reg dest,
+ void math(GenReg dest,
uint32_t function,
uint32_t saturate,
uint32_t msg_reg_nr,
- brw_reg src,
+ GenReg src,
uint32_t data_type,
uint32_t precision);
- void brw_math2(brw_reg dest, uint32_t function, brw_reg src0, brw_reg src1);
- void brw_EOT(uint32_t msg_nr);
+ void math2(GenReg dest, uint32_t function, GenReg src0, GenReg src1);
+ void EOT(uint32_t msg_nr);
- void brw_dword_scattered_read(brw_reg dest, brw_reg mrf, uint32_t bind_table_index);
+ void dword_scattered_read(GenReg dest, GenReg mrf, uint32_t bind_table_index);
- void brw_land_fwd_jump(int jmp_insn_idx);
- void brw_NOP(void);
- void brw_WAIT(void);
+ void land_fwd_jump(int jmp_insn_idx);
+ void NOP(void);
+ void WAIT(void);
- void brw_CMP(brw_reg dest, uint32_t conditional, brw_reg src0, brw_reg src1);
- void brw_copy_indirect_to_indirect(brw_indirect dst_ptr, brw_indirect src_ptr, uint32_t count);
- void brw_copy_from_indirect(brw_reg dst, brw_indirect ptr, uint32_t count);
- void brw_copy4(brw_reg dst, brw_reg src, uint32_t count);
- void brw_copy8(brw_reg dst, brw_reg src, uint32_t count);
- void brw_math_invert(brw_reg dst, brw_reg src);
- void brw_set_src1(brw_instruction *insn, brw_reg reg);
- void brw_set_uip_jip(void);
+ void CMP(GenReg dest, uint32_t conditional, GenReg src0, GenReg src1);
+ void copy_indirect_to_indirect(GenIndirect dst_ptr, GenIndirect src_ptr, uint32_t count);
+ void copy_from_indirect(GenReg dst, GenIndirect ptr, uint32_t count);
+ void copy4(GenReg dst, GenReg src, uint32_t count);
+ void copy8(GenReg dst, GenReg src, uint32_t count);
+ void math_invert(GenReg dst, GenReg src);
+ void set_src1(GenInstruction *insn, GenReg reg);
+ void set_uip_jip(void);
};
-void brw_print_reg(brw_reg reg);
+void brw_print_reg(GenReg reg);
-static inline int type_sz(uint32_t type)
+static INLINE int type_sz(uint32_t type)
{
switch(type) {
- case BRW_REGISTER_TYPE_UD:
- case BRW_REGISTER_TYPE_D:
- case BRW_REGISTER_TYPE_F:
+ case GEN_REGISTER_TYPE_UD:
+ case GEN_REGISTER_TYPE_D:
+ case GEN_REGISTER_TYPE_F:
return 4;
- case BRW_REGISTER_TYPE_HF:
- case BRW_REGISTER_TYPE_UW:
- case BRW_REGISTER_TYPE_W:
+ case GEN_REGISTER_TYPE_HF:
+ case GEN_REGISTER_TYPE_UW:
+ case GEN_REGISTER_TYPE_W:
return 2;
- case BRW_REGISTER_TYPE_UB:
- case BRW_REGISTER_TYPE_B:
+ case GEN_REGISTER_TYPE_UB:
+ case GEN_REGISTER_TYPE_B:
return 1;
default:
return 0;
}
/**
- * Construct a brw_reg.
- * \param file one of the BRW_x_REGISTER_FILE values
+ * Construct a GenReg.
+ * \param file one of the GEN_x_REGISTER_FILE values
* \param nr register number/index
* \param subnr register sub number
- * \param type one of BRW_REGISTER_TYPE_x
- * \param vstride one of BRW_VERTICAL_STRIDE_x
- * \param width one of BRW_WIDTH_x
- * \param hstride one of BRW_HORIZONTAL_STRIDE_x
- * \param swizzle one of BRW_SWIZZLE_x
+ * \param type one of GEN_REGISTER_TYPE_x
+ * \param vstride one of GEN_VERTICAL_STRIDE_x
+ * \param width one of GEN_WIDTH_x
+ * \param hstride one of GEN_HORIZONTAL_STRIDE_x
+ * \param swizzle one of GEN_SWIZZLE_x
* \param writemask WRITEMASK_X/Y/Z/W bitfield
*/
-static inline brw_reg make_brw_reg(uint32_t file,
+static INLINE GenReg makeGenReg(uint32_t file,
uint32_t nr,
uint32_t subnr,
uint32_t type,
uint32_t swizzle,
uint32_t writemask)
{
- struct brw_reg reg;
- if (file == BRW_GENERAL_REGISTER_FILE)
- assert(nr < BRW_MAX_GRF);
- else if (file == BRW_ARCHITECTURE_REGISTER_FILE)
- assert(nr <= BRW_ARF_IP);
+ GenReg reg;
+ if (file == GEN_GENERAL_REGISTER_FILE)
+ assert(nr < GEN_MAX_GRF);
+ else if (file == GEN_ARCHITECTURE_REGISTER_FILE)
+ assert(nr <= GEN_ARF_IP);
reg.type = type;
reg.file = file;
reg.vstride = vstride;
reg.width = width;
reg.hstride = hstride;
- reg.address_mode = BRW_ADDRESS_DIRECT;
+ reg.address_mode = GEN_ADDRESS_DIRECT;
reg.pad0 = 0;
/* Could do better: If the reg is r5.3<0;1,0>, we probably want to
}
/** Construct float[16] register */
-static inline brw_reg brw_vec16_reg(uint32_t file, uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec16_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return make_brw_reg(file,
+ return makeGenReg(file,
nr,
subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_16,
- BRW_WIDTH_16,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYZW,
+ GEN_REGISTER_TYPE_F,
+ GEN_VERTICAL_STRIDE_16,
+ GEN_WIDTH_16,
+ GEN_HORIZONTAL_STRIDE_1,
+ GEN_SWIZZLE_XYZW,
WRITEMASK_XYZW);
}
/** Construct float[8] register */
-static inline brw_reg brw_vec8_reg(uint32_t file, uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec8_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return make_brw_reg(file,
+ return makeGenReg(file,
nr,
subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_8,
- BRW_WIDTH_8,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYZW,
+ GEN_REGISTER_TYPE_F,
+ GEN_VERTICAL_STRIDE_8,
+ GEN_WIDTH_8,
+ GEN_HORIZONTAL_STRIDE_1,
+ GEN_SWIZZLE_XYZW,
WRITEMASK_XYZW);
}
/** Construct float[4] register */
-static inline brw_reg brw_vec4_reg(uint32_t file, uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec4_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return make_brw_reg(file,
+ return makeGenReg(file,
nr,
subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_4,
- BRW_WIDTH_4,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYZW,
+ GEN_REGISTER_TYPE_F,
+ GEN_VERTICAL_STRIDE_4,
+ GEN_WIDTH_4,
+ GEN_HORIZONTAL_STRIDE_1,
+ GEN_SWIZZLE_XYZW,
WRITEMASK_XYZW);
}
/** Construct float[2] register */
-static inline brw_reg brw_vec2_reg(uint32_t file, uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec2_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return make_brw_reg(file,
+ return makeGenReg(file,
nr,
subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_2,
- BRW_WIDTH_2,
- BRW_HORIZONTAL_STRIDE_1,
- BRW_SWIZZLE_XYXY,
+ GEN_REGISTER_TYPE_F,
+ GEN_VERTICAL_STRIDE_2,
+ GEN_WIDTH_2,
+ GEN_HORIZONTAL_STRIDE_1,
+ GEN_SWIZZLE_XYXY,
WRITEMASK_XY);
}
/** Construct float[1] register */
-static inline brw_reg brw_vec1_reg(uint32_t file, uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec1_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return make_brw_reg(file,
+ return makeGenReg(file,
nr,
subnr,
- BRW_REGISTER_TYPE_F,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_XXXX,
+ GEN_REGISTER_TYPE_F,
+ GEN_VERTICAL_STRIDE_0,
+ GEN_WIDTH_1,
+ GEN_HORIZONTAL_STRIDE_0,
+ GEN_SWIZZLE_XXXX,
WRITEMASK_X);
}
-static inline brw_reg retype(brw_reg reg, uint32_t type)
+static INLINE GenReg retype(GenReg reg, uint32_t type)
{
reg.type = type;
return reg;
}
-static inline brw_reg sechalf(brw_reg reg)
+static INLINE GenReg sechalf(GenReg reg)
{
if (reg.vstride)
reg.nr++;
return reg;
}
-static inline brw_reg suboffset(brw_reg reg, uint32_t delta)
+static INLINE GenReg suboffset(GenReg reg, uint32_t delta)
{
reg.subnr += delta * type_sz(reg.type);
return reg;
}
-static inline brw_reg offset(brw_reg reg, uint32_t delta)
+static INLINE GenReg offset(GenReg reg, uint32_t delta)
{
reg.nr += delta;
return reg;
}
-static inline brw_reg byte_offset(brw_reg reg, uint32_t bytes)
+static INLINE GenReg byte_offset(GenReg reg, uint32_t bytes)
{
uint32_t newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
reg.nr = newoffset / REG_SIZE;
/** Construct unsigned word[16] register */
-static inline brw_reg brw_uw16_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static INLINE GenReg brw_uw16_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
+ return suboffset(retype(brw_vec16_reg(file, nr, 0), GEN_REGISTER_TYPE_UW), subnr);
}
/** Construct unsigned word[8] register */
-static inline brw_reg brw_uw8_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static INLINE GenReg brw_uw8_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
+ return suboffset(retype(brw_vec8_reg(file, nr, 0), GEN_REGISTER_TYPE_UW), subnr);
}
/** Construct unsigned word[1] register */
-static inline brw_reg brw_uw1_reg(uint32_t file,
- uint32_t nr,
- uint32_t subnr)
+static INLINE GenReg brw_uw1_reg(uint32_t file, uint32_t nr, uint32_t subnr)
{
- return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
+ return suboffset(retype(brw_vec1_reg(file, nr, 0), GEN_REGISTER_TYPE_UW), subnr);
}
-static inline brw_reg brw_imm_reg(uint32_t type)
+static INLINE GenReg brw_imm_reg(uint32_t type)
{
- return make_brw_reg(BRW_IMMEDIATE_VALUE,
+ return makeGenReg(GEN_IMMEDIATE_VALUE,
0,
0,
type,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
+ GEN_VERTICAL_STRIDE_0,
+ GEN_WIDTH_1,
+ GEN_HORIZONTAL_STRIDE_0,
0,
0);
}
/** Construct float immediate register */
-static inline brw_reg brw_imm_f(float f)
+static INLINE GenReg brw_imm_f(float f)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_F);
imm.dw1.f = f;
return imm;
}
/** Construct integer immediate register */
-static inline brw_reg brw_imm_d(int d)
+static INLINE GenReg brw_imm_d(int d)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_D);
imm.dw1.d = d;
return imm;
}
/** Construct uint immediate register */
-static inline brw_reg brw_imm_ud(uint32_t ud)
+static INLINE GenReg brw_imm_ud(uint32_t ud)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_UD);
imm.dw1.ud = ud;
return imm;
}
/** Construct ushort immediate register */
-static inline brw_reg brw_imm_uw(uint16_t uw)
+static INLINE GenReg brw_imm_uw(uint16_t uw)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_UW);
imm.dw1.ud = uw | (uw << 16);
return imm;
}
/** Construct short immediate register */
-static inline brw_reg brw_imm_w(short w)
+static INLINE GenReg brw_imm_w(short w)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_W);
imm.dw1.d = w | (w << 16);
return imm;
}
*/
/** Construct vector of eight signed half-byte values */
-static inline brw_reg brw_imm_v(uint32_t v)
+static INLINE GenReg brw_imm_v(uint32_t v)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
- imm.vstride = BRW_VERTICAL_STRIDE_0;
- imm.width = BRW_WIDTH_8;
- imm.hstride = BRW_HORIZONTAL_STRIDE_1;
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_V);
+ imm.vstride = GEN_VERTICAL_STRIDE_0;
+ imm.width = GEN_WIDTH_8;
+ imm.hstride = GEN_HORIZONTAL_STRIDE_1;
imm.dw1.ud = v;
return imm;
}
/** Construct vector of four 8-bit float values */
-static inline brw_reg brw_imm_vf(uint32_t v)
+static INLINE GenReg brw_imm_vf(uint32_t v)
{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
- imm.vstride = BRW_VERTICAL_STRIDE_0;
- imm.width = BRW_WIDTH_4;
- imm.hstride = BRW_HORIZONTAL_STRIDE_1;
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_VF);
+ imm.vstride = GEN_VERTICAL_STRIDE_0;
+ imm.width = GEN_WIDTH_4;
+ imm.hstride = GEN_HORIZONTAL_STRIDE_1;
imm.dw1.ud = v;
return imm;
}
#define VF_ONE 0x30
#define VF_NEG (1<<7)
-static inline brw_reg brw_imm_vf4(uint32_t v0,
- uint32_t v1,
- uint32_t v2,
- uint32_t v3)
-{
- brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
- imm.vstride = BRW_VERTICAL_STRIDE_0;
- imm.width = BRW_WIDTH_4;
- imm.hstride = BRW_HORIZONTAL_STRIDE_1;
- imm.dw1.ud = ((v0 << 0) |
- (v1 << 8) |
- (v2 << 16) |
- (v3 << 24));
+static INLINE GenReg brw_imm_vf4(uint32_t v0, uint32_t v1, uint32_t v2, uint32_t v3)
+{
+ GenReg imm = brw_imm_reg(GEN_REGISTER_TYPE_VF);
+ imm.vstride = GEN_VERTICAL_STRIDE_0;
+ imm.width = GEN_WIDTH_4;
+ imm.hstride = GEN_HORIZONTAL_STRIDE_1;
+ imm.dw1.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24));
return imm;
}
-static inline brw_reg brw_address(brw_reg reg)
+static INLINE GenReg brw_address(GenReg reg)
{
return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
}
/** Construct float[1] general-purpose register */
-static inline brw_reg brw_vec1_grf(uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec1_grf(uint32_t nr, uint32_t subnr)
{
- return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+ return brw_vec1_reg(GEN_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct float[2] general-purpose register */
-static inline brw_reg brw_vec2_grf(uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec2_grf(uint32_t nr, uint32_t subnr)
{
- return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+ return brw_vec2_reg(GEN_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct float[4] general-purpose register */
-static inline brw_reg brw_vec4_grf(uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec4_grf(uint32_t nr, uint32_t subnr)
{
- return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+ return brw_vec4_reg(GEN_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct float[8] general-purpose register */
-static inline brw_reg brw_vec8_grf(uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_vec8_grf(uint32_t nr, uint32_t subnr)
{
- return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+ return brw_vec8_reg(GEN_GENERAL_REGISTER_FILE, nr, subnr);
}
-static inline brw_reg brw_uw8_grf(uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_uw8_grf(uint32_t nr, uint32_t subnr)
{
- return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+ return brw_uw8_reg(GEN_GENERAL_REGISTER_FILE, nr, subnr);
}
-static inline brw_reg brw_uw16_grf(uint32_t nr, uint32_t subnr)
+static INLINE GenReg brw_uw16_grf(uint32_t nr, uint32_t subnr)
{
- return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
+ return brw_uw16_reg(GEN_GENERAL_REGISTER_FILE, nr, subnr);
}
/** Construct null register (usually used for setting condition codes) */
-static inline brw_reg brw_null_reg(void)
+static INLINE GenReg brw_null_reg(void)
{
- return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_NULL,
+ return brw_vec8_reg(GEN_ARCHITECTURE_REGISTER_FILE,
+ GEN_ARF_NULL,
0);
}
-static inline brw_reg brw_address_reg(uint32_t subnr)
+static INLINE GenReg brw_address_reg(uint32_t subnr)
{
- return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_ADDRESS,
+ return brw_uw1_reg(GEN_ARCHITECTURE_REGISTER_FILE,
+ GEN_ARF_ADDRESS,
subnr);
}
* aren't xyzw. This goes against the convention for other scalar
* regs:
*/
-static inline brw_reg brw_ip_reg(void)
+static INLINE GenReg brw_ip_reg(void)
{
- return make_brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_IP,
+ return makeGenReg(GEN_ARCHITECTURE_REGISTER_FILE,
+ GEN_ARF_IP,
0,
- BRW_REGISTER_TYPE_UD,
- BRW_VERTICAL_STRIDE_4, /* ? */
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_XYZW, /* NOTE! */
+ GEN_REGISTER_TYPE_UD,
+ GEN_VERTICAL_STRIDE_4, /* ? */
+ GEN_WIDTH_1,
+ GEN_HORIZONTAL_STRIDE_0,
+ GEN_SWIZZLE_XYZW, /* NOTE! */
WRITEMASK_XYZW); /* NOTE! */
}
-static inline brw_reg brw_acc_reg(void)
+static INLINE GenReg brw_acc_reg(void)
{
- return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_ACCUMULATOR,
+ return brw_vec8_reg(GEN_ARCHITECTURE_REGISTER_FILE,
+ GEN_ARF_ACCUMULATOR,
0);
}
-static inline brw_reg brw_notification_1_reg(void)
+static INLINE GenReg brw_notification_1_reg(void)
{
- return make_brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
- BRW_ARF_NOTIFICATION_COUNT,
+ return makeGenReg(GEN_ARCHITECTURE_REGISTER_FILE,
+ GEN_ARF_NOTIFICATION_COUNT,
1,
- BRW_REGISTER_TYPE_UD,
- BRW_VERTICAL_STRIDE_0,
- BRW_WIDTH_1,
- BRW_HORIZONTAL_STRIDE_0,
- BRW_SWIZZLE_XXXX,
+ GEN_REGISTER_TYPE_UD,
+ GEN_VERTICAL_STRIDE_0,
+ GEN_WIDTH_1,
+ GEN_HORIZONTAL_STRIDE_0,
+ GEN_SWIZZLE_XXXX,
WRITEMASK_X);
}
-static inline brw_reg brw_flag_reg(void)
+static INLINE GenReg brw_flag_reg(void)
{
- return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_FLAG, 0);
+ return brw_uw1_reg(GEN_ARCHITECTURE_REGISTER_FILE, GEN_ARF_FLAG, 0);
}
-static inline brw_reg brw_mask_reg(uint32_t subnr)
+static INLINE GenReg brw_mask_reg(uint32_t subnr)
{
- return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr);
+ return brw_uw1_reg(GEN_ARCHITECTURE_REGISTER_FILE, GEN_ARF_MASK, subnr);
}
/* This is almost always called with a numeric constant argument, so
* make things easy to evaluate at compile time:
*/
-static inline uint32_t cvt(uint32_t val)
+static INLINE uint32_t cvt(uint32_t val)
{
switch (val) {
case 0: return 0;
return 0;
}
-static inline brw_reg stride(brw_reg reg,
+static INLINE GenReg stride(GenReg reg,
uint32_t vstride,
uint32_t width,
uint32_t hstride)
}
-static inline brw_reg vec16(brw_reg reg)
+static INLINE GenReg vec16(GenReg reg)
{
return stride(reg, 16,16,1);
}
-static inline brw_reg vec8(brw_reg reg)
+static INLINE GenReg vec8(GenReg reg)
{
return stride(reg, 8,8,1);
}
-static inline brw_reg vec4(brw_reg reg)
+static INLINE GenReg vec4(GenReg reg)
{
return stride(reg, 4,4,1);
}
-static inline brw_reg vec2(brw_reg reg)
+static INLINE GenReg vec2(GenReg reg)
{
return stride(reg, 2,2,1);
}
-static inline brw_reg vec1(brw_reg reg)
+static INLINE GenReg vec1(GenReg reg)
{
return stride(reg, 0,1,0);
}
-static inline brw_reg get_element(brw_reg reg, uint32_t elt)
+static INLINE GenReg get_element(GenReg reg, uint32_t elt)
{
return vec1(suboffset(reg, elt));
}
-static inline brw_reg get_element_ud(brw_reg reg, uint32_t elt)
+static INLINE GenReg get_element_ud(GenReg reg, uint32_t elt)
{
- return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
+ return vec1(suboffset(retype(reg, GEN_REGISTER_TYPE_UD), elt));
}
-static inline brw_reg get_element_d(brw_reg reg, uint32_t elt)
+static INLINE GenReg get_element_d(GenReg reg, uint32_t elt)
{
- return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt));
+ return vec1(suboffset(retype(reg, GEN_REGISTER_TYPE_D), elt));
}
-static inline brw_reg brw_swizzle(brw_reg reg, uint32_t x, uint32_t y, uint32_t z, uint32_t w)
+static INLINE GenReg brw_swizzle(GenReg reg, uint32_t x, uint32_t y, uint32_t z, uint32_t w)
{
- assert(reg.file != BRW_IMMEDIATE_VALUE);
- reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
- BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
- BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
- BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
+ assert(reg.file != GEN_IMMEDIATE_VALUE);
+ reg.dw1.bits.swizzle = GEN_SWIZZLE4(GEN_GET_SWZ(reg.dw1.bits.swizzle, x),
+ GEN_GET_SWZ(reg.dw1.bits.swizzle, y),
+ GEN_GET_SWZ(reg.dw1.bits.swizzle, z),
+ GEN_GET_SWZ(reg.dw1.bits.swizzle, w));
return reg;
}
-static inline brw_reg brw_swizzle1(brw_reg reg, uint32_t x)
+static INLINE GenReg brw_swizzle1(GenReg reg, uint32_t x)
{
return brw_swizzle(reg, x, x, x, x);
}
-static inline brw_reg brw_writemask(brw_reg reg, uint32_t mask)
+static INLINE GenReg brw_writemask(GenReg reg, uint32_t mask)
{
- assert(reg.file != BRW_IMMEDIATE_VALUE);
+ assert(reg.file != GEN_IMMEDIATE_VALUE);
reg.dw1.bits.writemask &= mask;
return reg;
}
-static inline brw_reg brw_set_writemask(brw_reg reg, uint32_t mask)
+static INLINE GenReg brw_set_writemask(GenReg reg, uint32_t mask)
{
- assert(reg.file != BRW_IMMEDIATE_VALUE);
+ assert(reg.file != GEN_IMMEDIATE_VALUE);
reg.dw1.bits.writemask = mask;
return reg;
}
-static inline brw_reg negate(brw_reg reg)
+static INLINE GenReg negate(GenReg reg)
{
reg.negate ^= 1;
return reg;
}
-static inline brw_reg brw_abs(brw_reg reg)
+static INLINE GenReg brw_abs(GenReg reg)
{
reg.abs = 1;
reg.negate = 0;
return reg;
}
-static inline brw_reg brw_vec4_indirect(uint32_t subnr, int offset)
+static INLINE GenReg brw_vec4_indirect(uint32_t subnr, int offset)
{
- brw_reg reg = brw_vec4_grf(0, 0);
+ GenReg reg = brw_vec4_grf(0, 0);
reg.subnr = subnr;
- reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
+ reg.address_mode = GEN_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
return reg;
}
-static inline brw_reg brw_vec1_indirect(uint32_t subnr, int offset)
+static INLINE GenReg brw_vec1_indirect(uint32_t subnr, int offset)
{
- brw_reg reg = brw_vec1_grf(0, 0);
+ GenReg reg = brw_vec1_grf(0, 0);
reg.subnr = subnr;
- reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
+ reg.address_mode = GEN_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
return reg;
}
-static inline brw_reg deref_4f(brw_indirect ptr, int offset)
+static INLINE GenReg deref_4f(GenIndirect ptr, int offset)
{
return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
}
-static inline brw_reg deref_1f(brw_indirect ptr, int offset)
+static INLINE GenReg deref_1f(GenIndirect ptr, int offset)
{
return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
}
-static inline brw_reg deref_4b(brw_indirect ptr, int offset)
+static INLINE GenReg deref_4b(GenIndirect ptr, int offset)
{
- return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
+ return retype(deref_4f(ptr, offset), GEN_REGISTER_TYPE_B);
}
-static inline brw_reg deref_1uw(brw_indirect ptr, int offset)
+static INLINE GenReg deref_1uw(GenIndirect ptr, int offset)
{
- return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
+ return retype(deref_1f(ptr, offset), GEN_REGISTER_TYPE_UW);
}
-static inline brw_reg deref_1d(brw_indirect ptr, int offset)
+static INLINE GenReg deref_1d(GenIndirect ptr, int offset)
{
- return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
+ return retype(deref_1f(ptr, offset), GEN_REGISTER_TYPE_D);
}
-static inline brw_reg deref_1ud(brw_indirect ptr, int offset)
+static INLINE GenReg deref_1ud(GenIndirect ptr, int offset)
{
- return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
+ return retype(deref_1f(ptr, offset), GEN_REGISTER_TYPE_UD);
}
-static inline brw_reg get_addr_reg(brw_indirect ptr)
+static INLINE GenReg get_addr_reg(GenIndirect ptr)
{
return brw_address_reg(ptr.addr_subnr);
}
-static inline brw_indirect brw_indirect_offset(brw_indirect ptr, int offset)
+static INLINE GenIndirect GenIndirect_offset(GenIndirect ptr, int offset)
{
ptr.addr_offset += offset;
return ptr;
}
-static inline brw_indirect make_brw_indirect(uint32_t addr_subnr, int offset)
+static INLINE GenIndirect make_GenIndirect(uint32_t addr_subnr, int offset)
{
- brw_indirect ptr;
+ GenIndirect ptr;
ptr.addr_subnr = addr_subnr;
ptr.addr_offset = offset;
ptr.pad = 0;
return ptr;
}
-static inline bool
-brw_same_reg(brw_reg r1, brw_reg r2)
+static INLINE bool
+brw_same_reg(GenReg r1, GenReg r2)
{
return r1.file == r2.file && r1.nr == r2.nr;
}
uint32_t brw_swap_cmod(uint32_t cmod);
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* BRW_EU_H */
+#endif /* GEN_EU_H */
#define Elements(x) (sizeof(x) / sizeof(*(x)))
-void brw_compile::guess_execution_size(brw_instruction *insn, brw_reg reg)
+void GenEmitter::guess_execution_size(GenInstruction *insn, GenReg reg)
{
- if (reg.width == BRW_WIDTH_8 && this->compressed)
- insn->header.execution_size = BRW_EXECUTE_16;
+ if (reg.width == GEN_WIDTH_8 && this->compressed)
+ insn->header.execution_size = GEN_EXECUTE_16;
else
insn->header.execution_size = reg.width; /* note - definitions are compatible */
}
uint32_t brw_swap_cmod(uint32_t cmod)
{
switch (cmod) {
- case BRW_CONDITIONAL_Z:
- case BRW_CONDITIONAL_NZ:
+ case GEN_CONDITIONAL_Z:
+ case GEN_CONDITIONAL_NZ:
return cmod;
- case BRW_CONDITIONAL_G:
- return BRW_CONDITIONAL_LE;
- case BRW_CONDITIONAL_GE:
- return BRW_CONDITIONAL_L;
- case BRW_CONDITIONAL_L:
- return BRW_CONDITIONAL_GE;
- case BRW_CONDITIONAL_LE:
- return BRW_CONDITIONAL_G;
+ case GEN_CONDITIONAL_G:
+ return GEN_CONDITIONAL_LE;
+ case GEN_CONDITIONAL_GE:
+ return GEN_CONDITIONAL_L;
+ case GEN_CONDITIONAL_L:
+ return GEN_CONDITIONAL_GE;
+ case GEN_CONDITIONAL_LE:
+ return GEN_CONDITIONAL_G;
default:
return ~0;
}
/* How does predicate control work when execution_size != 8? Do I
* need to test/set for 0xffff when execution_size is 16?
*/
-void brw_compile::brw_set_predicate_control_flag_value(uint32_t value)
+void GenEmitter::set_predicate_control_flag_value(uint32_t value)
{
if (value != 0xff) {
if (value != this->flag_value) {
- this->brw_MOV(brw_flag_reg(), brw_imm_uw(value));
+ this->MOV(brw_flag_reg(), brw_imm_uw(value));
this->flag_value = value;
}
}
}
-void brw_compile::brw_set_predicate_control(uint32_t pc)
+void GenEmitter::set_predicate_control(uint32_t pc)
{
// p->current->header.predicate_control = pc;
}
-void brw_compile::brw_set_predicate_inverse(bool predicate_inverse)
+void GenEmitter::set_predicate_inverse(bool predicate_inverse)
{
// p->current->header.predicate_inverse = predicate_inverse;
}
-void brw_compile::brw_set_conditionalmod(uint32_t conditional)
+void GenEmitter::set_conditionalmod(uint32_t conditional)
{
// p->current->header.destreg__conditionalmod = conditional;
}
-void brw_compile::brw_set_access_mode(uint32_t access_mode)
+void GenEmitter::set_access_mode(uint32_t access_mode)
{
// p->current->header.access_mode = access_mode;
}
void
-brw_compile::brw_set_compression_control(enum brw_compression compression_control)
+GenEmitter::set_compression_control(enum brw_compression compression_control)
{
#if 0
- p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
+ p->compressed = (compression_control == GEN_COMPRESSION_COMPRESSED);
if (p->gen >= 6) {
/* Since we don't use the 32-wide support in gen6, we translate
* the pre-gen6 compression control here.
*/
switch (compression_control) {
- case BRW_COMPRESSION_NONE:
+ case GEN_COMPRESSION_NONE:
/* This is the "use the first set of bits of dmask/vmask/arf
* according to execsize" option.
*/
p->current->header.compression_control = GEN6_COMPRESSION_1Q;
break;
- case BRW_COMPRESSION_2NDHALF:
+ case GEN_COMPRESSION_2NDHALF:
/* For 8-wide, this is "use the second set of 8 bits." */
p->current->header.compression_control = GEN6_COMPRESSION_2Q;
break;
- case BRW_COMPRESSION_COMPRESSED:
+ case GEN_COMPRESSION_COMPRESSED:
/* For 16-wide instruction compression, use the first set of 16 bits
* since we don't do 32-wide dispatch.
*/
#endif
}
-void brw_compile::brw_set_dest(brw_instruction *insn, brw_reg dest)
+void GenEmitter::set_dest(GenInstruction *insn, GenReg dest)
{
- if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE)
+ if (dest.file != GEN_ARCHITECTURE_REGISTER_FILE)
assert(dest.nr < 128);
insn->bits1.da1.dest_reg_file = dest.file;
insn->bits1.da1.dest_reg_type = dest.type;
insn->bits1.da1.dest_address_mode = dest.address_mode;
- if (dest.address_mode == BRW_ADDRESS_DIRECT) {
+ if (dest.address_mode == GEN_ADDRESS_DIRECT) {
insn->bits1.da1.dest_reg_nr = dest.nr;
- if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (insn->header.access_mode == GEN_ALIGN_1) {
insn->bits1.da1.dest_subreg_nr = dest.subnr;
- if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
- dest.hstride = BRW_HORIZONTAL_STRIDE_1;
+ if (dest.hstride == GEN_HORIZONTAL_STRIDE_0)
+ dest.hstride = GEN_HORIZONTAL_STRIDE_1;
insn->bits1.da1.dest_horiz_stride = dest.hstride;
}
else {
/* These are different sizes in align1 vs align16:
*/
- if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (insn->header.access_mode == GEN_ALIGN_1) {
insn->bits1.ia1.dest_indirect_offset = dest.dw1.bits.indirect_offset;
- if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
- dest.hstride = BRW_HORIZONTAL_STRIDE_1;
+ if (dest.hstride == GEN_HORIZONTAL_STRIDE_0)
+ dest.hstride = GEN_HORIZONTAL_STRIDE_1;
insn->bits1.ia1.dest_horiz_stride = dest.hstride;
}
else {
static const int reg_type_size[8] = { 4, 4, 2, 2, 1, 1, 4 };
static void
-validate_reg(brw_instruction *insn, brw_reg reg)
+validate_reg(GenInstruction *insn, GenReg reg)
{
int hstride_for_reg[] = {0, 1, 2, 4};
int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
int execsize_for_reg[] = {1, 2, 4, 8, 16};
int width, hstride, vstride, execsize;
- if (reg.file == BRW_IMMEDIATE_VALUE) {
+ if (reg.file == GEN_IMMEDIATE_VALUE) {
/* 3.3.6: Region Parameters. Restriction: Immediate vectors
* mean the destination has to be 128-bit aligned and the
* destination horiz stride has to be a word.
*/
- if (reg.type == BRW_REGISTER_TYPE_V) {
+ if (reg.type == GEN_REGISTER_TYPE_V) {
assert(hstride_for_reg[insn->bits1.da1.dest_horiz_stride] *
reg_type_size[insn->bits1.da1.dest_reg_type] == 2);
}
return;
}
- if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
- reg.file == BRW_ARF_NULL)
+ if (reg.file == GEN_ARCHITECTURE_REGISTER_FILE &&
+ reg.file == GEN_ARF_NULL)
return;
assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg));
}
void
-brw_compile::brw_set_src0(brw_instruction *insn, brw_reg reg)
+GenEmitter::set_src0(GenInstruction *insn, GenReg reg)
{
- if (reg.type != BRW_ARCHITECTURE_REGISTER_FILE)
+ if (reg.type != GEN_ARCHITECTURE_REGISTER_FILE)
assert(reg.nr < 128);
validate_reg(insn, reg);
insn->bits2.da1.src0_negate = reg.negate;
insn->bits2.da1.src0_address_mode = reg.address_mode;
- if (reg.file == BRW_IMMEDIATE_VALUE) {
+ if (reg.file == GEN_IMMEDIATE_VALUE) {
insn->bits3.ud = reg.dw1.ud;
/* Required to set some fields in src1 as well:
}
else
{
- if (reg.address_mode == BRW_ADDRESS_DIRECT) {
- if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (reg.address_mode == GEN_ADDRESS_DIRECT) {
+ if (insn->header.access_mode == GEN_ALIGN_1) {
insn->bits2.da1.src0_subreg_nr = reg.subnr;
insn->bits2.da1.src0_reg_nr = reg.nr;
}
else {
insn->bits2.ia1.src0_subreg_nr = reg.subnr;
- if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (insn->header.access_mode == GEN_ALIGN_1) {
insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
}
else {
}
}
- if (insn->header.access_mode == BRW_ALIGN_1) {
- if (reg.width == BRW_WIDTH_1 &&
- insn->header.execution_size == BRW_EXECUTE_1) {
- insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
- insn->bits2.da1.src0_width = BRW_WIDTH_1;
- insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
+ if (insn->header.access_mode == GEN_ALIGN_1) {
+ if (reg.width == GEN_WIDTH_1 &&
+ insn->header.execution_size == GEN_EXECUTE_1) {
+ insn->bits2.da1.src0_horiz_stride = GEN_HORIZONTAL_STRIDE_0;
+ insn->bits2.da1.src0_width = GEN_WIDTH_1;
+ insn->bits2.da1.src0_vert_stride = GEN_VERTICAL_STRIDE_0;
}
else {
insn->bits2.da1.src0_horiz_stride = reg.hstride;
}
}
else {
- insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
- insn->bits2.da16.src0_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
- insn->bits2.da16.src0_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z);
- insn->bits2.da16.src0_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W);
+ insn->bits2.da16.src0_swz_x = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_X);
+ insn->bits2.da16.src0_swz_y = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_Y);
+ insn->bits2.da16.src0_swz_z = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_Z);
+ insn->bits2.da16.src0_swz_w = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_W);
/* This is an oddity of the fact we're using the same
* descriptions for registers in align_16 as align_1:
*/
- if (reg.vstride == BRW_VERTICAL_STRIDE_8)
- insn->bits2.da16.src0_vert_stride = BRW_VERTICAL_STRIDE_4;
+ if (reg.vstride == GEN_VERTICAL_STRIDE_8)
+ insn->bits2.da16.src0_vert_stride = GEN_VERTICAL_STRIDE_4;
else
insn->bits2.da16.src0_vert_stride = reg.vstride;
}
}
-void brw_compile::brw_set_src1(
- brw_instruction *insn,
- brw_reg reg)
+void GenEmitter::set_src1(GenInstruction *insn, GenReg reg)
{
assert(reg.nr < 128);
/* Only src1 can be immediate in two-argument instructions.
*/
- assert(insn->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE);
+ assert(insn->bits1.da1.src0_reg_file != GEN_IMMEDIATE_VALUE);
- if (reg.file == BRW_IMMEDIATE_VALUE) {
+ if (reg.file == GEN_IMMEDIATE_VALUE) {
insn->bits3.ud = reg.dw1.ud;
}
else {
/* This is a hardware restriction, which may or may not be lifted
* in the future:
*/
- assert (reg.address_mode == BRW_ADDRESS_DIRECT);
- /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
+ assert (reg.address_mode == GEN_ADDRESS_DIRECT);
+ /* assert (reg.file == GEN_GENERAL_REGISTER_FILE); */
- if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (insn->header.access_mode == GEN_ALIGN_1) {
insn->bits3.da1.src1_subreg_nr = reg.subnr;
insn->bits3.da1.src1_reg_nr = reg.nr;
}
insn->bits3.da16.src1_reg_nr = reg.nr;
}
- if (insn->header.access_mode == BRW_ALIGN_1) {
- if (reg.width == BRW_WIDTH_1 &&
- insn->header.execution_size == BRW_EXECUTE_1) {
- insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
- insn->bits3.da1.src1_width = BRW_WIDTH_1;
- insn->bits3.da1.src1_vert_stride = BRW_VERTICAL_STRIDE_0;
+ if (insn->header.access_mode == GEN_ALIGN_1) {
+ if (reg.width == GEN_WIDTH_1 &&
+ insn->header.execution_size == GEN_EXECUTE_1) {
+ insn->bits3.da1.src1_horiz_stride = GEN_HORIZONTAL_STRIDE_0;
+ insn->bits3.da1.src1_width = GEN_WIDTH_1;
+ insn->bits3.da1.src1_vert_stride = GEN_VERTICAL_STRIDE_0;
}
else {
insn->bits3.da1.src1_horiz_stride = reg.hstride;
}
}
else {
- insn->bits3.da16.src1_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
- insn->bits3.da16.src1_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
- insn->bits3.da16.src1_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z);
- insn->bits3.da16.src1_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W);
+ insn->bits3.da16.src1_swz_x = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_X);
+ insn->bits3.da16.src1_swz_y = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_Y);
+ insn->bits3.da16.src1_swz_z = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_Z);
+ insn->bits3.da16.src1_swz_w = GEN_GET_SWZ(reg.dw1.bits.swizzle, GEN_CHANNEL_W);
/* This is an oddity of the fact we're using the same
* descriptions for registers in align_16 as align_1:
*/
- if (reg.vstride == BRW_VERTICAL_STRIDE_8)
- insn->bits3.da16.src1_vert_stride = BRW_VERTICAL_STRIDE_4;
+ if (reg.vstride == GEN_VERTICAL_STRIDE_8)
+ insn->bits3.da16.src1_vert_stride = GEN_VERTICAL_STRIDE_4;
else
insn->bits3.da16.src1_vert_stride = reg.vstride;
}
* choose not to fill in irrelevant bits; they will be zero.
*/
static void
-brw_set_message_descriptor(brw_compile *p,
- brw_instruction *inst,
+brw_set_message_descriptor(GenEmitter *p,
+ GenInstruction *inst,
enum brw_message_target sfid,
unsigned msg_length,
unsigned response_length,
bool header_present,
bool end_of_thread)
{
- p->brw_set_src1(inst, brw_imm_d(0));
+ p->set_src1(inst, brw_imm_d(0));
if (p->gen >= 5) {
inst->bits3.generic_gen5.header_present = header_present;
}
}
-static void brw_set_math_message(brw_compile *p,
- brw_instruction *insn,
+static void brw_set_math_message(GenEmitter *p,
+ GenInstruction *insn,
uint32_t function,
uint32_t integer_type,
bool low_precision,
/* Infer message length from the function */
switch (function) {
- case BRW_MATH_FUNCTION_POW:
- case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT:
- case BRW_MATH_FUNCTION_INT_DIV_REMAINDER:
- case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
+ case GEN_MATH_FUNCTION_POW:
+ case GEN_MATH_FUNCTION_INT_DIV_QUOTIENT:
+ case GEN_MATH_FUNCTION_INT_DIV_REMAINDER:
+ case GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
msg_length = 2;
break;
default:
/* Infer response length from the function */
switch (function) {
- case BRW_MATH_FUNCTION_SINCOS:
- case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
+ case GEN_MATH_FUNCTION_SINCOS:
+ case GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
response_length = 2;
break;
default:
break;
}
- brw_set_message_descriptor(p, insn, BRW_SFID_MATH,
+ brw_set_message_descriptor(p, insn, GEN_SFID_MATH,
msg_length, response_length, false, false);
if (p->gen == 5) {
insn->bits3.math_gen5.function = function;
}
void
-brw_compile::brw_set_dp_write_message(brw_instruction *insn,
- uint32_t binding_table_index,
- uint32_t msg_control,
- uint32_t msg_type,
- uint32_t msg_length,
- bool header_present,
- uint32_t last_render_target,
- uint32_t response_length,
- uint32_t end_of_thread,
- uint32_t send_commit_msg)
+GenEmitter::set_dp_write_message(GenInstruction *insn,
+ uint32_t binding_table_index,
+ uint32_t msg_control,
+ uint32_t msg_type,
+ uint32_t msg_length,
+ bool header_present,
+ uint32_t last_render_target,
+ uint32_t response_length,
+ uint32_t end_of_thread,
+ uint32_t send_commit_msg)
{
unsigned sfid;
}
void
-brw_compile::brw_set_dp_read_message(brw_instruction *insn,
+GenEmitter::set_dp_read_message(GenInstruction *insn,
uint32_t binding_table_index,
uint32_t msg_control,
uint32_t msg_type,
}
void
-brw_compile::brw_set_sampler_message(brw_instruction *insn,
+GenEmitter::set_sampler_message(GenInstruction *insn,
uint32_t binding_table_index,
uint32_t sampler,
uint32_t msg_type,
uint32_t simd_mode,
uint32_t return_format)
{
- brw_set_message_descriptor(this, insn, BRW_SFID_SAMPLER, msg_length,
+ brw_set_message_descriptor(this, insn, GEN_SFID_SAMPLER, msg_length,
response_length, header_present, false);
insn->bits3.sampler_gen7.binding_table_index = binding_table_index;
insn->bits3.sampler_gen7.sampler = sampler;
insn->bits3.sampler_gen7.simd_mode = simd_mode;
}
-#define next_insn brw_next_insn
-brw_instruction *
-brw_compile::brw_next_insn(uint32_t opcode)
+GenInstruction *GenEmitter::next_insn(uint32_t opcode)
{
- brw_instruction *insn;
+ GenInstruction *insn;
insn = &this->store[this->nr_insn++];
insn->header.opcode = opcode;
return insn;
}
-static brw_instruction *brw_alu1(brw_compile *p,
+static GenInstruction *brw_alu1(GenEmitter *p,
uint32_t opcode,
- brw_reg dest,
- brw_reg src)
+ GenReg dest,
+ GenReg src)
{
- brw_instruction *insn = p->next_insn(opcode);
- p->brw_set_dest(insn, dest);
- p->brw_set_src0(insn, src);
+ GenInstruction *insn = p->next_insn(opcode);
+ p->set_dest(insn, dest);
+ p->set_src0(insn, src);
return insn;
}
-static brw_instruction *brw_alu2(brw_compile *p,
+static GenInstruction *brw_alu2(GenEmitter *p,
uint32_t opcode,
- brw_reg dest,
- brw_reg src0,
- brw_reg src1)
+ GenReg dest,
+ GenReg src0,
+ GenReg src1)
{
- brw_instruction *insn = p->next_insn(opcode);
- p->brw_set_dest(insn, dest);
- p->brw_set_src0(insn, src0);
- p->brw_set_src1(insn, src1);
+ GenInstruction *insn = p->next_insn(opcode);
+ p->set_dest(insn, dest);
+ p->set_src0(insn, src0);
+ p->set_src1(insn, src1);
return insn;
}
static int
-get_3src_subreg_nr(brw_reg reg)
+get_3src_subreg_nr(GenReg reg)
{
- if (reg.vstride == BRW_VERTICAL_STRIDE_0) {
+ if (reg.vstride == GEN_VERTICAL_STRIDE_0) {
assert(brw_is_single_value_swizzle(reg.dw1.bits.swizzle));
- return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0);
+ return reg.subnr / 4 + GEN_GET_SWZ(reg.dw1.bits.swizzle, 0);
} else
return reg.subnr / 4;
}
-static brw_instruction *brw_alu3(brw_compile *p,
+static GenInstruction *brw_alu3(GenEmitter *p,
uint32_t opcode,
- brw_reg dest,
- brw_reg src0,
- brw_reg src1,
- brw_reg src2)
+ GenReg dest,
+ GenReg src0,
+ GenReg src1,
+ GenReg src2)
{
- brw_instruction *insn = p->next_insn(opcode);
+ GenInstruction *insn = p->next_insn(opcode);
- assert(insn->header.access_mode == BRW_ALIGN_16);
+ assert(insn->header.access_mode == GEN_ALIGN_16);
- assert(dest.file == BRW_GENERAL_REGISTER_FILE);
+ assert(dest.file == GEN_GENERAL_REGISTER_FILE);
assert(dest.nr < 128);
- assert(dest.address_mode == BRW_ADDRESS_DIRECT);
- assert(dest.type = BRW_REGISTER_TYPE_F);
+ assert(dest.address_mode == GEN_ADDRESS_DIRECT);
+ assert(dest.type = GEN_REGISTER_TYPE_F);
insn->bits1.da3src.dest_reg_file = 0;
insn->bits1.da3src.dest_reg_nr = dest.nr;
insn->bits1.da3src.dest_subreg_nr = dest.subnr / 16;
insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask;
p->guess_execution_size(insn, dest);
- assert(src0.file == BRW_GENERAL_REGISTER_FILE);
- assert(src0.address_mode == BRW_ADDRESS_DIRECT);
+ assert(src0.file == GEN_GENERAL_REGISTER_FILE);
+ assert(src0.address_mode == GEN_ADDRESS_DIRECT);
assert(src0.nr < 128);
- assert(src0.type == BRW_REGISTER_TYPE_F);
+ assert(src0.type == GEN_REGISTER_TYPE_F);
insn->bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
insn->bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
insn->bits2.da3src.src0_reg_nr = src0.nr;
insn->bits1.da3src.src0_abs = src0.abs;
insn->bits1.da3src.src0_negate = src0.negate;
- insn->bits2.da3src.src0_rep_ctrl = src0.vstride == BRW_VERTICAL_STRIDE_0;
+ insn->bits2.da3src.src0_rep_ctrl = src0.vstride == GEN_VERTICAL_STRIDE_0;
- assert(src1.file == BRW_GENERAL_REGISTER_FILE);
- assert(src1.address_mode == BRW_ADDRESS_DIRECT);
+ assert(src1.file == GEN_GENERAL_REGISTER_FILE);
+ assert(src1.address_mode == GEN_ADDRESS_DIRECT);
assert(src1.nr < 128);
- assert(src1.type == BRW_REGISTER_TYPE_F);
+ assert(src1.type == GEN_REGISTER_TYPE_F);
insn->bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
insn->bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) & 0x3;
insn->bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) >> 2;
- insn->bits2.da3src.src1_rep_ctrl = src1.vstride == BRW_VERTICAL_STRIDE_0;
+ insn->bits2.da3src.src1_rep_ctrl = src1.vstride == GEN_VERTICAL_STRIDE_0;
insn->bits3.da3src.src1_reg_nr = src1.nr;
insn->bits1.da3src.src1_abs = src1.abs;
insn->bits1.da3src.src1_negate = src1.negate;
- assert(src2.file == BRW_GENERAL_REGISTER_FILE);
- assert(src2.address_mode == BRW_ADDRESS_DIRECT);
+ assert(src2.file == GEN_GENERAL_REGISTER_FILE);
+ assert(src2.address_mode == GEN_ADDRESS_DIRECT);
assert(src2.nr < 128);
- assert(src2.type == BRW_REGISTER_TYPE_F);
+ assert(src2.type == GEN_REGISTER_TYPE_F);
insn->bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
insn->bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
- insn->bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
+ insn->bits3.da3src.src2_rep_ctrl = src2.vstride == GEN_VERTICAL_STRIDE_0;
insn->bits3.da3src.src2_reg_nr = src2.nr;
insn->bits1.da3src.src2_abs = src2.abs;
insn->bits1.da3src.src2_negate = src2.negate;
* Convenience routines.
*/
#define ALU1(OP) \
-brw_instruction *brw_compile::brw_##OP(brw_reg dest, brw_reg src0) \
+GenInstruction *GenEmitter::OP(GenReg dest, GenReg src0) \
{ \
- return brw_alu1(this, BRW_OPCODE_##OP, dest, src0); \
+ return brw_alu1(this, GEN_OPCODE_##OP, dest, src0); \
}
#define ALU2(OP) \
-brw_instruction *brw_compile::brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1) \
+GenInstruction *GenEmitter::OP(GenReg dest, GenReg src0, GenReg src1) \
{ \
- return brw_alu2(this, BRW_OPCODE_##OP, dest, src0, src1); \
+ return brw_alu2(this, GEN_OPCODE_##OP, dest, src0, src1); \
}
#define ALU3(OP) \
-brw_instruction *brw_compile::brw_##OP(brw_reg dest, brw_reg src0, brw_reg src1, brw_reg src2) \
+GenInstruction *GenEmitter::OP(GenReg dest, GenReg src0, GenReg src1, GenReg src2) \
{ \
- return brw_alu3(this, BRW_OPCODE_##OP, dest, src0, src1, src2); \
+ return brw_alu3(this, GEN_OPCODE_##OP, dest, src0, src1, src2); \
}
/* Rounding operations (other than RNDD) require two instructions - the first
* Sandybridge and later appear to round correctly without an ADD.
*/
#define ROUND(OP) \
-void brw_compile::brw_##OP(brw_reg dest, brw_reg src) \
+void GenEmitter::OP(GenReg dest, GenReg src) \
{ \
- brw_instruction *rnd; \
- rnd = this->next_insn(BRW_OPCODE_##OP); \
- this->brw_set_dest(rnd, dest); \
- this->brw_set_src0(rnd, src); \
+ GenInstruction *rnd; \
+ rnd = this->next_insn(GEN_OPCODE_##OP); \
+ this->set_dest(rnd, dest); \
+ this->set_src0(rnd, src); \
}
ALU1(MOV)
ROUND(RNDZ)
ROUND(RNDE)
-brw_instruction *brw_compile::brw_ADD(
- brw_reg dest,
- brw_reg src0,
- brw_reg src1)
+GenInstruction *GenEmitter::ADD(GenReg dest, GenReg src0, GenReg src1)
{
/* 6.2.2: add */
- if (src0.type == BRW_REGISTER_TYPE_F ||
- (src0.file == BRW_IMMEDIATE_VALUE &&
- src0.type == BRW_REGISTER_TYPE_VF)) {
- assert(src1.type != BRW_REGISTER_TYPE_UD);
- assert(src1.type != BRW_REGISTER_TYPE_D);
+ if (src0.type == GEN_REGISTER_TYPE_F ||
+ (src0.file == GEN_IMMEDIATE_VALUE &&
+ src0.type == GEN_REGISTER_TYPE_VF)) {
+ assert(src1.type != GEN_REGISTER_TYPE_UD);
+ assert(src1.type != GEN_REGISTER_TYPE_D);
}
- if (src1.type == BRW_REGISTER_TYPE_F ||
- (src1.file == BRW_IMMEDIATE_VALUE &&
- src1.type == BRW_REGISTER_TYPE_VF)) {
- assert(src0.type != BRW_REGISTER_TYPE_UD);
- assert(src0.type != BRW_REGISTER_TYPE_D);
+ if (src1.type == GEN_REGISTER_TYPE_F ||
+ (src1.file == GEN_IMMEDIATE_VALUE &&
+ src1.type == GEN_REGISTER_TYPE_VF)) {
+ assert(src0.type != GEN_REGISTER_TYPE_UD);
+ assert(src0.type != GEN_REGISTER_TYPE_D);
}
- return brw_alu2(this, BRW_OPCODE_ADD, dest, src0, src1);
+ return brw_alu2(this, GEN_OPCODE_ADD, dest, src0, src1);
}
-brw_instruction *brw_compile::brw_MUL(
- brw_reg dest,
- brw_reg src0,
- brw_reg src1)
+GenInstruction *GenEmitter::MUL(GenReg dest, GenReg src0, GenReg src1)
{
/* 6.32.38: mul */
- if (src0.type == BRW_REGISTER_TYPE_D ||
- src0.type == BRW_REGISTER_TYPE_UD ||
- src1.type == BRW_REGISTER_TYPE_D ||
- src1.type == BRW_REGISTER_TYPE_UD) {
- assert(dest.type != BRW_REGISTER_TYPE_F);
+ if (src0.type == GEN_REGISTER_TYPE_D ||
+ src0.type == GEN_REGISTER_TYPE_UD ||
+ src1.type == GEN_REGISTER_TYPE_D ||
+ src1.type == GEN_REGISTER_TYPE_UD) {
+ assert(dest.type != GEN_REGISTER_TYPE_F);
}
- if (src0.type == BRW_REGISTER_TYPE_F ||
- (src0.file == BRW_IMMEDIATE_VALUE &&
- src0.type == BRW_REGISTER_TYPE_VF)) {
- assert(src1.type != BRW_REGISTER_TYPE_UD);
- assert(src1.type != BRW_REGISTER_TYPE_D);
+ if (src0.type == GEN_REGISTER_TYPE_F ||
+ (src0.file == GEN_IMMEDIATE_VALUE &&
+ src0.type == GEN_REGISTER_TYPE_VF)) {
+ assert(src1.type != GEN_REGISTER_TYPE_UD);
+ assert(src1.type != GEN_REGISTER_TYPE_D);
}
- if (src1.type == BRW_REGISTER_TYPE_F ||
- (src1.file == BRW_IMMEDIATE_VALUE &&
- src1.type == BRW_REGISTER_TYPE_VF)) {
- assert(src0.type != BRW_REGISTER_TYPE_UD);
- assert(src0.type != BRW_REGISTER_TYPE_D);
+ if (src1.type == GEN_REGISTER_TYPE_F ||
+ (src1.file == GEN_IMMEDIATE_VALUE &&
+ src1.type == GEN_REGISTER_TYPE_VF)) {
+ assert(src0.type != GEN_REGISTER_TYPE_UD);
+ assert(src0.type != GEN_REGISTER_TYPE_D);
}
- assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
- src0.nr != BRW_ARF_ACCUMULATOR);
- assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE ||
- src1.nr != BRW_ARF_ACCUMULATOR);
+ assert(src0.file != GEN_ARCHITECTURE_REGISTER_FILE ||
+ src0.nr != GEN_ARF_ACCUMULATOR);
+ assert(src1.file != GEN_ARCHITECTURE_REGISTER_FILE ||
+ src1.nr != GEN_ARF_ACCUMULATOR);
- return brw_alu2(this, BRW_OPCODE_MUL, dest, src0, src1);
+ return brw_alu2(this, GEN_OPCODE_MUL, dest, src0, src1);
}
-void brw_compile::brw_NOP(void)
+void GenEmitter::NOP(void)
{
- brw_instruction *insn = this->next_insn(BRW_OPCODE_NOP);
- this->brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- this->brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- this->brw_set_src1(insn, brw_imm_ud(0x0));
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_NOP);
+ this->set_dest(insn, retype(brw_vec4_grf(0,0), GEN_REGISTER_TYPE_UD));
+ this->set_src0(insn, retype(brw_vec4_grf(0,0), GEN_REGISTER_TYPE_UD));
+ this->set_src1(insn, brw_imm_ud(0x0));
}
-brw_instruction *brw_compile::brw_JMPI(
- brw_reg dest,
- brw_reg src0,
- brw_reg src1)
+GenInstruction *GenEmitter::JMPI(GenReg dest, GenReg src0, GenReg src1)
{
- brw_instruction *insn = brw_alu2(this, BRW_OPCODE_JMPI, dest, src0, src1);
-
+ GenInstruction *insn = brw_alu2(this, GEN_OPCODE_JMPI, dest, src0, src1);
insn->header.execution_size = 1;
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.mask_control = BRW_MASK_DISABLE;
-
- // this->current->header.predicate_control = BRW_PREDICATE_NONE;
-
+ insn->header.compression_control = GEN_COMPRESSION_NONE;
+ insn->header.mask_control = GEN_MASK_DISABLE;
return insn;
}
* instruction should populate the flag register. It might be simpler
* just to use the flag reg for most WM tasks?
*/
-void brw_compile::brw_CMP(
- brw_reg dest,
- uint32_t conditional,
- brw_reg src0,
- brw_reg src1)
+void GenEmitter::CMP(GenReg dest, uint32_t conditional, GenReg src0, GenReg src1)
{
- brw_instruction *insn = this->next_insn(BRW_OPCODE_CMP);
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_CMP);
insn->header.destreg__conditionalmod = conditional;
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, src0);
- this->brw_set_src1(insn, src1);
+ this->set_dest(insn, dest);
+ this->set_src0(insn, src0);
+ this->set_src1(insn, src1);
/* guess_execution_size(insn, src0); */
#if 0
* value until brw_set_predicate_control_flag_value() is called
* again.
*/
- if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ if (dest.file == GEN_ARCHITECTURE_REGISTER_FILE &&
dest.nr == 0) {
- this->current->header.predicate_control = BRW_PREDICATE_NORMAL;
+ this->current->header.predicate_control = GEN_PREDICATE_NORMAL;
this->flag_value = 0xff;
}
#endif
/* Issue 'wait' instruction for n1, host could program MMIO
to wake up thread. */
-void brw_compile::brw_WAIT(void)
+void GenEmitter::WAIT(void)
{
- brw_instruction *insn = this->next_insn(BRW_OPCODE_WAIT);
- brw_reg src = brw_notification_1_reg();
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_WAIT);
+ GenReg src = brw_notification_1_reg();
- this->brw_set_dest(insn, src);
- this->brw_set_src0(insn, src);
- this->brw_set_src1(insn, brw_null_reg());
+ this->set_dest(insn, src);
+ this->set_src0(insn, src);
+ this->set_src1(insn, brw_null_reg());
insn->header.execution_size = 0; /* must */
insn->header.predicate_control = 0;
insn->header.compression_control = 0;
}
/* Extended math function, float[8] */
-void brw_compile::brw_math(
- brw_reg dest,
+void GenEmitter::math(
+ GenReg dest,
uint32_t function,
uint32_t saturate,
uint32_t msg_reg_nr,
- brw_reg src,
+ GenReg src,
uint32_t data_type,
uint32_t precision)
{
if (this->gen >= 6) {
- brw_instruction *insn = this->next_insn(BRW_OPCODE_MATH);
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_MATH);
- assert(dest.file == BRW_GENERAL_REGISTER_FILE);
- assert(src.file == BRW_GENERAL_REGISTER_FILE);
+ assert(dest.file == GEN_GENERAL_REGISTER_FILE);
+ assert(src.file == GEN_GENERAL_REGISTER_FILE);
- assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
+ assert(dest.hstride == GEN_HORIZONTAL_STRIDE_1);
if (this->gen == 6)
- assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
+ assert(src.hstride == GEN_HORIZONTAL_STRIDE_1);
/* Source modifiers are ignored for extended math instructions on Gen6. */
if (this->gen == 6) {
assert(!src.abs);
}
- if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
- function == BRW_MATH_FUNCTION_INT_DIV_REMAINDER ||
- function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
- assert(src.type != BRW_REGISTER_TYPE_F);
+ if (function == GEN_MATH_FUNCTION_INT_DIV_QUOTIENT ||
+ function == GEN_MATH_FUNCTION_INT_DIV_REMAINDER ||
+ function == GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
+ assert(src.type != GEN_REGISTER_TYPE_F);
} else {
- assert(src.type == BRW_REGISTER_TYPE_F);
+ assert(src.type == GEN_REGISTER_TYPE_F);
}
/* Math is the same ISA format as other opcodes, except that CondModifier
insn->header.destreg__conditionalmod = function;
insn->header.saturate = saturate;
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, src);
- this->brw_set_src1(insn, brw_null_reg());
+ this->set_dest(insn, dest);
+ this->set_src0(insn, src);
+ this->set_src1(insn, brw_null_reg());
} else {
- brw_instruction *insn = this->next_insn(BRW_OPCODE_SEND);
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_SEND);
/* Example code doesn't set predicate_control for send
* instructions.
insn->header.predicate_control = 0;
insn->header.destreg__conditionalmod = msg_reg_nr;
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, src);
+ this->set_dest(insn, dest);
+ this->set_src0(insn, src);
brw_set_math_message(this,
insn,
function,
- src.type == BRW_REGISTER_TYPE_D,
+ src.type == GEN_REGISTER_TYPE_D,
precision,
saturate,
data_type);
}
/* Extended math function, float[8] */
-void brw_compile::brw_math2(brw_reg dest,
+void GenEmitter::math2(GenReg dest,
uint32_t function,
- brw_reg src0,
- brw_reg src1)
+ GenReg src0,
+ GenReg src1)
{
- brw_instruction *insn = this->next_insn(BRW_OPCODE_MATH);
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_MATH);
assert(this->gen >= 6);
- assert(dest.file == BRW_GENERAL_REGISTER_FILE);
- assert(src0.file == BRW_GENERAL_REGISTER_FILE);
- assert(src1.file == BRW_GENERAL_REGISTER_FILE);
+ assert(dest.file == GEN_GENERAL_REGISTER_FILE);
+ assert(src0.file == GEN_GENERAL_REGISTER_FILE);
+ assert(src1.file == GEN_GENERAL_REGISTER_FILE);
- assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
+ assert(dest.hstride == GEN_HORIZONTAL_STRIDE_1);
if (this->gen == 6) {
- assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1);
- assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1);
+ assert(src0.hstride == GEN_HORIZONTAL_STRIDE_1);
+ assert(src1.hstride == GEN_HORIZONTAL_STRIDE_1);
}
- if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
- function == BRW_MATH_FUNCTION_INT_DIV_REMAINDER ||
- function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
- assert(src0.type != BRW_REGISTER_TYPE_F);
- assert(src1.type != BRW_REGISTER_TYPE_F);
+ if (function == GEN_MATH_FUNCTION_INT_DIV_QUOTIENT ||
+ function == GEN_MATH_FUNCTION_INT_DIV_REMAINDER ||
+ function == GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
+ assert(src0.type != GEN_REGISTER_TYPE_F);
+ assert(src1.type != GEN_REGISTER_TYPE_F);
} else {
- assert(src0.type == BRW_REGISTER_TYPE_F);
- assert(src1.type == BRW_REGISTER_TYPE_F);
+ assert(src0.type == GEN_REGISTER_TYPE_F);
+ assert(src1.type == GEN_REGISTER_TYPE_F);
}
/* Source modifiers are ignored for extended math instructions on Gen6. */
*/
insn->header.destreg__conditionalmod = function;
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, src0);
- this->brw_set_src1(insn, src1);
+ this->set_dest(insn, dest);
+ this->set_src0(insn, src0);
+ this->set_src1(insn, src1);
}
/* Extended math function, float[16] */
-void brw_compile::brw_math_16(brw_reg dest,
+void GenEmitter::math_16(GenReg dest,
uint32_t function,
uint32_t saturate,
uint32_t msg_reg_nr,
- brw_reg src,
+ GenReg src,
uint32_t precision)
{
- brw_instruction *insn;
+ GenInstruction *insn;
- insn = this->next_insn(BRW_OPCODE_MATH);
+ insn = this->next_insn(GEN_OPCODE_MATH);
/* Math is the same ISA format as other opcodes, except that CondModifier
* becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
assert(!src.negate);
assert(!src.abs);
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, src);
- this->brw_set_src1(insn, brw_null_reg());
+ this->set_dest(insn, dest);
+ this->set_src0(insn, src);
+ this->set_src1(insn, brw_null_reg());
}
* Location (in buffer) appears as UD offsets in the register after
* the provided mrf header reg.
*/
-void brw_compile::brw_dword_scattered_read(
- brw_reg dest,
- brw_reg mrf,
- uint32_t bind_table_index)
+void GenEmitter::dword_scattered_read(GenReg dest, GenReg mrf, uint32_t bti)
{
- mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
+ mrf = retype(mrf, GEN_REGISTER_TYPE_UD);
- this->brw_set_predicate_control(BRW_PREDICATE_NONE);
- this->brw_set_compression_control(BRW_COMPRESSION_NONE);
- this->brw_MOV(mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+ this->set_predicate_control(GEN_PREDICATE_NONE);
+ this->set_compression_control(GEN_COMPRESSION_NONE);
+ this->MOV(mrf, retype(brw_vec8_grf(0, 0), GEN_REGISTER_TYPE_UD));
- brw_instruction *insn = this->next_insn(BRW_OPCODE_SEND);
+ GenInstruction *insn = this->next_insn(GEN_OPCODE_SEND);
insn->header.destreg__conditionalmod = mrf.nr;
/* cast dest to a uword[8] vector */
- dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
+ dest = retype(vec8(dest), GEN_REGISTER_TYPE_UW);
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, brw_null_reg());
+ this->set_dest(insn, dest);
+ this->set_src0(insn, brw_null_reg());
- this->brw_set_dp_read_message(insn,
- bind_table_index,
- BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS,
- BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ,
- BRW_DATAPORT_READ_TARGET_DATA_CACHE,
+ this->set_dp_read_message(insn,
+ bti,
+ GEN_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS,
+ GEN_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ,
+ GEN_DATAPORT_READ_TARGET_DATA_CACHE,
2, /* msg_length */
1); /* response_length */
}
* Note: the msg_type plus msg_length values determine exactly what kind
* of sampling operation is performed. See volume 4, page 161 of docs.
*/
-void brw_compile::brw_SAMPLE(
- brw_reg dest,
+void GenEmitter::SAMPLE(
+ GenReg dest,
uint32_t msg_reg_nr,
- brw_reg src0,
- uint32_t binding_table_index,
+ GenReg src0,
+ uint32_t bti,
uint32_t sampler,
uint32_t writemask,
uint32_t msg_type,
uint32_t simd_mode,
uint32_t return_format)
{
- bool need_stall = 0;
+ if (writemask == 0) return;
- if (writemask == 0) {
- /*printf("%s: zero writemask??\n", __FUNCTION__); */
- return;
- }
-
/* Hardware doesn't do destination dependency checking on send
* instructions properly. Add a workaround which generates the
* dependency by other means. In practice it seems like this bug
assert (writemask == WRITEMASK_XYZW);
{
- brw_instruction *insn;
+ GenInstruction *insn;
- insn = this->next_insn(BRW_OPCODE_SEND);
+ insn = this->next_insn(GEN_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
- insn->header.compression_control = BRW_COMPRESSION_NONE;
+ insn->header.compression_control = GEN_COMPRESSION_NONE;
if (this->gen < 6)
insn->header.destreg__conditionalmod = msg_reg_nr;
- this->brw_set_dest(insn, dest);
- this->brw_set_src0(insn, src0);
- this->brw_set_sampler_message(insn,
- binding_table_index,
+ this->set_dest(insn, dest);
+ this->set_src0(insn, src0);
+ this->set_sampler_message(insn,
+ bti,
sampler,
msg_type,
response_length,
simd_mode,
return_format);
}
-
- if (need_stall) {
- brw_reg reg = vec8(offset(dest, response_length-1));
-
- /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 } */
- this->brw_set_compression_control(BRW_COMPRESSION_NONE);
- this->brw_MOV(retype(reg, BRW_REGISTER_TYPE_UD),
- retype(reg, BRW_REGISTER_TYPE_UD));
- }
-
}
-void
-brw_compile::brw_EOT(uint32_t msg_nr)
+void GenEmitter::EOT(uint32_t msg_nr)
{
- brw_instruction *insn = NULL;
-
- insn = this->brw_MOV(brw_vec8_grf(msg_nr,0), brw_vec8_grf(0,0));
- insn->header.mask_control = BRW_MASK_DISABLE;
- insn = this->next_insn(BRW_OPCODE_SEND);
- this->brw_set_dest(insn, brw_null_reg());
- this->brw_set_src0(insn, brw_vec8_grf(msg_nr,0));
- this->brw_set_src1(insn, brw_imm_ud(0));
- insn->header.execution_size = BRW_EXECUTE_8;
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->bits3.spawner_gen5.resource = BRW_DO_NOT_DEREFERENCE_URB;
+ GenInstruction *insn = NULL;
+
+ insn = this->MOV(brw_vec8_grf(msg_nr,0), brw_vec8_grf(0,0));
+ insn->header.mask_control = GEN_MASK_DISABLE;
+ insn = this->next_insn(GEN_OPCODE_SEND);
+ this->set_dest(insn, brw_null_reg());
+ this->set_src0(insn, brw_vec8_grf(msg_nr,0));
+ this->set_src1(insn, brw_imm_ud(0));
+ insn->header.execution_size = GEN_EXECUTE_8;
+ insn->header.compression_control = GEN_COMPRESSION_NONE;
+ insn->bits3.spawner_gen5.resource = GEN_DO_NOT_DEREFERENCE_URB;
insn->bits3.spawner_gen5.msg_length = 1;
insn->bits3.spawner_gen5.end_of_thread = 1;
- insn->header.destreg__conditionalmod = BRW_SFID_THREAD_SPAWNER;
+ insn->header.destreg__conditionalmod = GEN_SFID_THREAD_SPAWNER;
}
+++ /dev/null
-/*
- * Copyright © 2012 Intel Corporation
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library. If not, see <http://www.gnu.org/licenses/>.
- *
- * Author: Benjamin Segovia <benjamin.segovia@intel.com>
- */
-
- /*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-#ifndef BRW_STRUCTS_H
-#define BRW_STRUCTS_H
-
-#include <stdint.h>
-
-#endif
void GenContext::emitCode(void) {
GenKernel *genKernel = static_cast<GenKernel*>(this->kernel);
- brw_compile *p = (brw_compile*) GBE_MALLOC(sizeof(brw_compile));
+ GenEmitter *p = (GenEmitter*) GBE_MALLOC(sizeof(GenEmitter));
std::memset(p, 0, sizeof(*p));
- p->brw_EOT(127);
+ p->EOT(127);
genKernel->insnNum = p->nr_insn;
- genKernel->insns = GBE_NEW_ARRAY(brw_instruction, genKernel->insnNum);
- std::memcpy(genKernel->insns, p->store, genKernel->insnNum * sizeof(brw_instruction));
+ genKernel->insns = GBE_NEW_ARRAY(GenInstruction, genKernel->insnNum);
+ std::memcpy(genKernel->insns, p->store, genKernel->insnNum * sizeof(GenInstruction));
GBE_FREE(p);
}
Kernel *GenContext::allocateKernel(void) {
{}
GenKernel::~GenKernel(void) { GBE_SAFE_DELETE_ARRAY(insns); }
const char *GenKernel::getCode(void) const { return (const char*) insns; }
- size_t GenKernel::getCodeSize(void) const { return insnNum * sizeof(brw_instruction); }
+ size_t GenKernel::getCodeSize(void) const { return insnNum * sizeof(GenInstruction); }
GenProgram::GenProgram(void) {}
GenProgram::~GenProgram(void) {}
#include "backend/program.hpp"
// Gen ISA instruction
-struct brw_instruction;
+struct GenInstruction;
namespace gbe
{
/*! Describe a compiled kernel */
virtual const char *getCode(void) const;
/*! Implements base class */
virtual size_t getCodeSize(void) const;
- brw_instruction *insns; //!< Instruction stream
+ GenInstruction *insns; //!< Instruction stream
uint32_t insnNum; //!< Number of instructions
GBE_STRUCT(GenKernel); //!< Use gbe allocators
};
#include "backend/program.h"
#include "backend/program.hpp"
-#include "backend/gen/brw_structs.h"
namespace gbe {
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