ARM i.MX5: Add system reset controller (SRC) to i.MX51 and i.MX53 device tree

Also, link SRC to IPU via phandle.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 76d84a4..0f6d331 100644 (file)
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -70,6 +70,7 @@
                        interrupts = <11 10>;
                        clocks = <&clks 59>, <&clks 110>, <&clks 61>;
                        clock-names = "bus", "di0", "di1";
+                       resets = <&src 2>;
                };
 
                aips@70000000 { /* AIPS1 */
@@ -529,6 +530,12 @@
                                status = "disabled";
                        };
 
+                       src: src@73fd0000 {
+                               compatible = "fsl,imx51-src";
+                               reg = <0x73fd0000 0x4000>;
+                               #reset-cells = <1>;
+                       };
+
                        clks: ccm@73fd4000{
                                compatible = "fsl,imx51-ccm";
                                reg = <0x73fd4000 0x4000>;

diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index d98350e..845982e 100644 (file)
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -75,6 +75,7 @@
                        interrupts = <11 10>;
                        clocks = <&clks 59>, <&clks 110>, <&clks 61>;
                        clock-names = "bus", "di0", "di1";
+                       resets = <&src 2>;
                };
 
                aips@50000000 { /* AIPS1 */
@@ -601,6 +602,12 @@
                                status = "disabled";
                        };
 
+                       src: src@53fd0000 {
+                               compatible = "fsl,imx53-src", "fsl,imx51-src";
+                               reg = <0x53fd0000 0x4000>;
+                               #reset-cells = <1>;
+                       };
+
                        clks: ccm@53fd4000{
                                compatible = "fsl,imx53-ccm";
                                reg = <0x53fd4000 0x4000>;