PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR

This fixes a minor regression where broken PCI devices that use the
reserved "11" memory BAR type worked before e354597cce but not after.

The low four bits of a memory BAR are "PTT0" where P=1 for prefetchable
BARs, and TT is as follows:

  00  32-bit BAR, anywhere in lower 4GB
  01  anywhere below 1MB (reserved as of PCI 2.2)
  10  64-bit BAR
  11  reserved

Prior to e354597cce, we treated "0100" as a 64-bit BAR and all others,
including prefetchable 64-bit BARs ("1100") as 32-bit BARs.  The e354597cce
fix, which appeared in 2.6.28, treats "x1x0" as 64-bit BARs, so the
reserved "x110" types are treated as 64-bit instead of 32-bit.

This patch returns to treating the reserved "11" type as a 32-bit BAR and
adds a warning if we see it.

It also logs a note if we see a 1M BAR.  This is not a warning, because
such hardware conforms to pre-PCI 2.2 spec, but I think it's worth noting
because Linux ignores the 1M restriction if it ever has to assign the BAR.

CC: Peter Chubb <peterc@gelato.unsw.edu.au>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=35952
Reported-by: Jan Zwiegers <jan@radicalsystems.co.za>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index f03ed96..3e7a00a 100644 (file)
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -100,8 +100,11 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
        return size;
 }
 
-static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
+static inline enum pci_bar_type decode_bar(struct pci_dev *dev,
+                                          struct resource *res, u32 bar)
 {
+       u32 mem_type;
+
        if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
                res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
                return pci_bar_io;
@@ -109,8 +112,21 @@ static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
 
        res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 
-       if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
+       mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
+       switch (mem_type) {
+       case PCI_BASE_ADDRESS_MEM_TYPE_32:
+               break;
+       case PCI_BASE_ADDRESS_MEM_TYPE_1M:
+               dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
+               break;
+       case PCI_BASE_ADDRESS_MEM_TYPE_64:
                return pci_bar_mem64;
+       default:
+               dev_warn(&dev->dev,
+                        "mem unknown type %x treated as 32-bit BAR\n",
+                        mem_type);
+               break;
+       }
        return pci_bar_mem32;
 }
 
@@ -164,7 +180,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                l = 0;
 
        if (type == pci_bar_unknown) {
-               type = decode_bar(res, l);
+               type = decode_bar(dev, res, l);
                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
                if (type == pci_bar_io) {
                        l &= PCI_BASE_ADDRESS_IO_MASK;