#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
+#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
#define PLL_NUM_OFFSET 0x10
#define PLL_DENOM_OFFSET 0x20
u32 enable_bit;
u32 div_mask;
u32 div_shift;
+ unsigned long ref_clock;
};
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
.set_rate = clk_pllv3_av_set_rate,
};
+static ulong clk_pllv3_enet_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+
+ return pll->ref_clock;
+}
+
+static const struct clk_ops clk_pllv3_enet_ops = {
+ .enable = clk_pllv3_generic_enable,
+ .disable = clk_pllv3_generic_disable,
+ .get_rate = clk_pllv3_enet_get_rate,
+};
+
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base,
u32 div_mask)
pll->div_shift = 0;
pll->powerup_set = false;
break;
+ case IMX_PLLV3_ENET:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_ENET;
+ pll->ref_clock = 500000000;
+ break;
default:
kfree(pll);
return ERR_PTR(-ENOTSUPP);
.ops = &clk_pllv3_av_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_pllv3_enet) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_ENET,
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_enet_ops,
+};