rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
}
+static void rtw_pci_clkreq_pad_low(struct rtw_dev *rtwdev, bool enable)
+{
+ u8 value;
+ int ret;
+
+ ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value);
+ if (ret) {
+ rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret);
+ return;
+ }
+
+ if (enable)
+ value &= ~BIT_CLKREQ_N_PAD;
+ else
+ value |= BIT_CLKREQ_N_PAD;
+
+ rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value);
+}
+
static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable)
{
u8 value;
static int __maybe_unused rtw_pci_suspend(struct device *dev)
{
+ struct ieee80211_hw *hw = dev_get_drvdata(dev);
+ struct rtw_dev *rtwdev = hw->priv;
+ struct rtw_chip_info *chip = rtwdev->chip;
+ struct rtw_efuse *efuse = &rtwdev->efuse;
+
+ if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6)
+ rtw_pci_clkreq_pad_low(rtwdev, true);
return 0;
}
static int __maybe_unused rtw_pci_resume(struct device *dev)
{
+ struct ieee80211_hw *hw = dev_get_drvdata(dev);
+ struct rtw_dev *rtwdev = hw->priv;
+ struct rtw_chip_info *chip = rtwdev->chip;
+ struct rtw_efuse *efuse = &rtwdev->efuse;
+
+ if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6)
+ rtw_pci_clkreq_pad_low(rtwdev, false);
return 0;
}