ARM: defconfig: enable I-Cache line size workaround on Exynos systems

All Exynos big.LITTLE system suffer from I-Cache line size mismatch between
CPU cores, so enable workaround for it in exynos_defconfig and
tizen_odroid_defconfig.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I0f324a5832e1ef47999f7b8d4ddd4a29db0ee176

diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 93c5182..24c6193 100644 (file)
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -10,6 +10,7 @@ CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS3=y
 CONFIG_EXYNOS5420_MCPM=y
+CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
 CONFIG_SMP=y
 CONFIG_BIG_LITTLE=y
 CONFIG_NR_CPUS=8

diff --git a/arch/arm/configs/tizen_odroid_defconfig b/arch/arm/configs/tizen_odroid_defconfig
index 73e5a96..17d7605 100644 (file)
--- a/arch/arm/configs/tizen_odroid_defconfig
+++ b/arch/arm/configs/tizen_odroid_defconfig
@@ -22,6 +22,7 @@ CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS3=y
 CONFIG_EXYNOS5420_MCPM=y
 # CONFIG_ARM_ERRATA_643719 is not set
+CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
 CONFIG_SMP=y
 CONFIG_BIG_LITTLE=y
 CONFIG_NR_CPUS=8