{
if ((isaFlag & hwIntrinsicInfoArray[i].isaflags) && strcmp(methodName, hwIntrinsicInfoArray[i].name) == 0)
{
- if (compSupports(isa))
+ if (compSupportsHWIntrinsic(isa))
{
// Intrinsic is supported on platform
result = hwIntrinsicInfoArray[i].id;
}
//------------------------------------------------------------------------
+// isFullyImplementedIsa: Gets a value that indicates whether the InstructionSet is fully implemented
+//
+// Arguments:
+// isa - The InstructionSet to check
+//
+// Return Value:
+// true if isa is supported; otherwise, false
+//
+// Notes:
+// This currently returns true for all partially-implemented ISAs.
+// TODO-Bug: Set this to return the correct values as GH 20427 is resolved.
+//
+bool HWIntrinsicInfo::isFullyImplementedIsa(InstructionSet isa)
+{
+ switch (isa)
+ {
+ case InstructionSet_Base:
+ case InstructionSet_Crc32:
+ case InstructionSet_Aes:
+ case InstructionSet_Simd:
+ case InstructionSet_Sha1:
+ case InstructionSet_Sha256:
+ return true;
+
+ default:
+ assert(!"Unexpected Arm64 HW intrinsics ISA");
+ return false;
+ }
+}
+
+//------------------------------------------------------------------------
+// isScalarIsa: Gets a value that indicates whether the InstructionSet is scalar
+//
+// Arguments:
+// isa - The InstructionSet to check
+//
+// Return Value:
+// true if isa is scalar; otherwise, false
+bool HWIntrinsicInfo::isScalarIsa(InstructionSet isa)
+{
+ switch (isa)
+ {
+ case InstructionSet_Base:
+ case InstructionSet_Crc32:
+ return true;
+
+ case InstructionSet_Aes:
+ case InstructionSet_Simd:
+ case InstructionSet_Sha1:
+ case InstructionSet_Sha256:
+ return false;
+
+ default:
+ assert(!"Unexpected Arm64 HW intrinsics ISA");
+ return true;
+ }
+}
+
+//------------------------------------------------------------------------
+// compSupportsHWIntrinsic: compiler support of hardware intrinsics
+//
+// Arguments:
+// isa - Instruction set
+// Return Value:
+// true if
+// - isa is a scalar ISA
+// - isa is a SIMD ISA and featureSIMD=true
+// - isa is fully implemented or EnableIncompleteISAClass=true
+bool Compiler::compSupportsHWIntrinsic(InstructionSet isa)
+{
+ return (featureSIMD || HWIntrinsicInfo::isScalarIsa(isa)) && (
+#ifdef DEBUG
+ JitConfig.EnableIncompleteISAClass() ||
+#endif
+ HWIntrinsicInfo::isFullyImplementedIsa(isa));
+}
+
+//------------------------------------------------------------------------
// lookupNumArgs: gets the number of arguments for the hardware intrinsic.
// This attempts to do a table based lookup but will fallback to the number
// of operands in 'node' if the table entry is -1.
// Simd instantiation type check
if (simdClass != nullptr)
{
- compFloatingPointUsed = true;
+ if (featureSIMD)
+ {
+ compFloatingPointUsed = true;
- simdBaseType = getBaseTypeAndSizeOfSIMDType(simdClass, &simdSizeBytes);
+ simdBaseType = getBaseTypeAndSizeOfSIMDType(simdClass, &simdSizeBytes);
+ }
if (simdBaseType == TYP_UNKNOWN)
{
- return impUnsupportedHWIntrinsic(CORINFO_HELP_THROW_TYPE_NOT_SUPPORTED, method, sig, mustExpand);
+ return impUnsupportedHWIntrinsic(CORINFO_HELP_THROW_PLATFORM_NOT_SUPPORTED, method, sig, mustExpand);
}
simdType = getSIMDTypeForSize(simdSizeBytes);
}
}
#endif // defined(_TARGET_X86_) || defined(_TARGET_AMD64_)
-#if defined(_TARGET_ARM64_) && defined(FEATURE_PAL)
- PAL_GetJitCpuCapabilityFlags(&CPUCompileFlags);
-#endif
-
#if defined(_TARGET_ARM64_)
static ConfigDWORD fFeatureSIMD;
if (fFeatureSIMD.val(CLRConfig::EXTERNAL_FeatureSIMD) != 0)
{
CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_FEATURE_SIMD);
}
-#endif
+#if defined(FEATURE_PAL)
+ PAL_GetJitCpuCapabilityFlags(&CPUCompileFlags);
+#elif defined(_WIN64)
+ // FP and SIMD support are enabled by default
+ CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_SIMD);
+ CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_FP);
+ // PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE (30)
+ if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
+ {
+ CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_AES);
+ CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_SHA1);
+ CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_SHA256);
+ }
+ // PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE (31)
+ if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
+ {
+ CPUCompileFlags.Set(CORJIT_FLAGS::CORJIT_FLAG_HAS_ARM64_CRC32);
+ }
+#endif // _WIN64
+#endif // _TARGET_ARM64_
m_CPUCompileFlags = CPUCompileFlags;
}
Func<TVectorType, TVectorType, TVectorType, TVectorTypeReturn> cryptoOp)
where TVectorType : new()
{
- TVectorType v = new TVectorType();
-
bool notSupported = false;
try
{
+ TVectorType v = new TVectorType();
cryptoOp(v,v,v);
}
catch (PlatformNotSupportedException) // TODO-Fixme check for Type not supported exception
testCryptoOp<uint, Vector128<uint>, uint, Vector128<uint> >(name, (x, y, z) => Sha1.SchedulePart2(x, y), sha1su2Res);
if(Sha1.FixedRotate(100) != 25)
throw new Exception("Sha1 FixedRotate failed.\n");
-
-
}
else
{