endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
-LIBS += cpu/mpc8xxx/ddr/libddr.a
-LIBS += cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a
+LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc86xx)
-LIBS += cpu/mpc8xxx/ddr/libddr.a
-LIBS += cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a
+LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
- @rm -f $(obj)cpu/mpc824x/bedbug_603e.c
+ @rm -f $(obj)arch/ppc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
the CPU's i2c node address).
- Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
+ Now, the u-boot i2c code for the mpc8xx (arch/ppc/cpu/mpc8xx/i2c.c)
sets the CPU up as a master node and so its address should
therefore be cleared to 0 (See, eg, MPC823e User's Manual
p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
- Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+ Overrides the default PCI memory map in arch/ppc/cpu/mpc8260/pci.c if set.
- CONFIG_PCI_DISABLE_PCIE:
Disable PCI-Express on systems where it is supported but not
COBJS-y += serial.o
COBJS-y += speed.o
COBJS-${CONFIG_FSL_DIU_FB} += diu.o
-COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
-COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_diu_fb.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../../../board/freescale/common/fsl_logo_bmp.o
COBJS-${CONFIG_CMD_IDE} += ide.o
COBJS-${CONFIG_IIM} += iim.o
COBJS-$(CONFIG_PCI) += pci.o
/*
- * needed for cpu/mpc512x/start.S
+ * needed for arch/ppc/cpu/mpc512x/start.S
*
* These should be auto-generated
*/
# Use default linker script.
# A board port can override this setting in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc512x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc512x/u-boot.lds
#include <command.h>
#include <asm/io.h>
-#include "../../board/freescale/common/fsl_diu_fb.h"
+#include "../../../../board/freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
#include <stdio_dev.h>
.plt : { *(.plt) }
.text :
{
- cpu/mpc512x/start.o (.text)
+ arch/ppc/cpu/mpc512x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
#
#
-# File: cpu/mpc5xx/Makefile
+# File: arch/ppc/cpu/mpc5xx/Makefile
#
# Discription: Makefile to build mpc5xx cpu configuration.
# Will include top config.mk which itselfs
-# uses the definitions made in cpu/mpc5xx/config.mk
+# uses the definitions made in arch/ppc/cpu/mpc5xx/config.mk
#
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xx/u-boot.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc5xx/start.o (.text)
+ arch/ppc/cpu/mpc5xx/start.o (.text)
*(.text)
*(.got1)
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc5xxx/start.o (.text)
- cpu/mpc5xxx/traps.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/traps.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/cache.o (.text)
arch/ppc/lib/time.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc8220/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8220/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc8220/start.o (.text)
+ arch/ppc/cpu/mpc8220/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc824x/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc8260/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc8260/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8260/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-ffixed-r2 -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc83xx/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc83xx/start.o (.text)
+ arch/ppc/cpu/mpc83xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/mpc85xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc85xx/u-boot.lds
.bootpg ADDR(.text) - 0x1000 :
{
- cpu/mpc85xx/start.o (.bootpg)
+ arch/ppc/cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
. = ADDR(.text) + 0x80000;
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
- cpu/mpc85xx/start.o (.bootpg)
+ arch/ppc/cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
.resetvec RESET_VECTOR_ADDRESS :
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
- * Basically this file contains cpu specific common code for 85xx/86xx
- * processors.
+ * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and
+ * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * cpu specific common code for 85xx/86xx processors.
* See file CREDITS for list of people who contributed to this
* project.
*
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
- * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
- * Basically this file contains cpu specific common code for 85xx/86xx
- * processors.
+ * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and
+ * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * cpu specific common code for 85xx/86xx processors.
* See file CREDITS for list of people who contributed to this
* project.
*
/*
- * cpu/ppc4xx/40x_spd_sdram.c
+ * arch/ppc/cpu/ppc4xx/40x_spd_sdram.c
* This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
* SDRAM controller. Those are all current 405 PPC's.
*
/*
- * cpu/ppc4xx/44x_spd_ddr.c
+ * arch/ppc/cpu/ppc4xx/44x_spd_ddr.c
* This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
* DDR controller. Those are 440GP/GX/EP/GR.
*
/*
- * cpu/ppc4xx/44x_spd_ddr2.c
+ * arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
/*
- * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+ * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
endif
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/cpu/ppc4xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/ppc4xx/u-boot.lds
/*
- * cpu/ppc4xx/denali_data_eye.c
+ * arch/ppc/cpu/ppc4xx/denali_data_eye.c
* Extracted from board/amcc/sequoia/sdram.c by Larry Johnson <lrj@acm.org>.
*
* (C) Copyright 2006
/*
- * cpu/ppc4xx/denali_spd_ddr2.c
+ * arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
* DDR2 controller, specifically the 440EPx/GRx.
*
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org.
*
- * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
+ * Based primarily on arch/ppc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
#ifdef CONFIG_440
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
/*
* PPC440 board need a board specific object with the
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
#define BOARD_ARCHES 4
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
#if defined(CONFIG_ARCHES)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x20000);
}
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_wrdtr(u32 default_val) {
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
}
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_clktr(u32 default_val) {
extern void denali_core_search_data_eye(void);
#if defined(CONFIG_NAND_SPL)
-/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+/* Using arch/ppc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
.plt : { *(.plt) }
.text :
{
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
}
/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
static int ppc440spe_rev_a(void)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/amirix/ap1000/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- cpu/mpc8xx/serial.o (.text)
- cpu/mpc8xx/cpu_init.o (.text)
- cpu/mpc8xx/speed.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/serial.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc8xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- cpu/mpc8xx/cpu.o (.text)
- cpu/mpc8xx/cpu_init.o (.text)
- cpu/mpc8xx/speed.o (.text)
- cpu/mpc8xx/serial.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc8xx/speed.o (.text)
+ arch/ppc/cpu/mpc8xx/serial.o (.text)
arch/ppc/lib/extable.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/string.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*. = DEFINED(env_offset) ? env_offset : .;*/
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
/*
* Configure the MPC8XX I/O ports per the ioport configuration table
- * (taken from ./cpu/mpc8260/cpu_init.c)
+ * (taken from ./arch/ppc/cpu/mpc8260/cpu_init.c)
*/
void config_mpc8xx_ioports (volatile immap_t * immr)
{
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o(.text)
+ arch/ppc/cpu/mpc8xx/start.o(.text)
*(.text)
common/env_embedded.o(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
arch/ppc/lib/time.o (.text)
arch/ppc/lib/ticks.o (.text)
arch/ppc/lib/cache.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
arch/ppc/lib/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
arch/ppc/lib/time.o (.text)
arch/ppc/lib/ticks.o (.text)
. = env_offset;
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8260/start.o (.text)
+ arch/ppc/cpu/mpc8260/start.o (.text)
/*
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
arch/ppc/lib/time.o (.text)
arch/ppc/lib/ticks.o (.text)
/**
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
arch/ppc/lib/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
arch/ppc/lib/time.o (.text)
arch/ppc/lib/ticks.o (.text)
/**
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on cpu/mpc8260/ether_scc.c.
+ * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on cpu/mpc8xx/scc.c.
+ * Based in part on arch/ppc/cpu/mpc8xx/scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on cpu/mpc8260/ether_scc.c.
+ * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
.bootpg 0xF7FBF000 :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
/*
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- * This file was adapted from cpu/mpc5xxx/serial.c
+ * This file was adapted from arch/ppc/cpu/mpc5xxx/serial.c
*
*/
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/ml2/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
arch/ppc/lib/board.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
PROVIDE(_f_init_rom = .);
.init : {
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
.plt : { *(.plt) }
.text :
{
- cpu/mpc824x/start.o (.text)
+ arch/ppc/cpu/mpc824x/start.o (.text)
common/board.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
.plt : { *(.plt) }
.text :
{
- cpu/mpc5xxx/start.o (.text)
+ arch/ppc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
Startup sequence
----------------
-(cpu/ppc4xx/resetvec.S)
+(arch/ppc/cpu/ppc4xx/resetvec.S)
depending on configs option
call _start_440 _start_pci oder _start
-(cpu/ppc4xx/start.S)
+(arch/ppc/cpu/ppc4xx/start.S)
_start_440:
initialize register like
* - board info struct
Save local variables to board info struct
call relocate_code() does not return
- relocate_code: (cpu/ppc4xx/start.S)
+ relocate_code: (arch/ppc/cpu/ppc4xx/start.S)
-------------------------------------------------------
From now on our copy is in RAM and we will run from there,
starting with board_init_r
flash_init: (board/netstal/hcu5/flash.c)
/* setup for u-boot erase, update */
setup bd flash info
- cpu_init_r: (cpu/ppc4xx/cpu_init.c)
+ cpu_init_r: (arch/ppc/cpu/ppc4xx/cpu_init.c)
peripheral chip select in using defines like
CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
mem_malloc_init
Most of the HW specific code for the HCU5 may be found in
include/configs/hcu5.h
board/netstal/hcu5/*
-cpu/ppc4xx/*
+arch/ppc/cpu/ppc4xx/*
arch/ppc/lib/*
include/ppc440.h
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
- * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
+ * GPIO's are alreay setup in arch/ppc/cpu/ppc4xx/cpu_init.c
* via define from board config file.
*-------------------------------------------------------------------*/
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- cpu/74xx_7xx/start.o (.text)
+ arch/ppc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/cpu_init.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
/***
. = env_offset;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8260/start.o (.text)
+ arch/ppc/cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
/*. = env_offset; */
*/
/*
- * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Ported from arch/ppc/cpu/ppc4xx/i2c.c by AS HARNOIS by
* Travis B. Sawyer
* Sandburst Corporation.
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/sandburst/karef/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/sandburst/metrobox/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/sc3/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
- cpu/mpc8xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc8xx/interrupts.o (.text)
arch/ppc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- cpu/mpc8xx/traps.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/ppc/cpu/ppc4xx
*/
sdram_init();
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
arch/ppc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
+ arch/ppc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/ppc4xx/start.o (.text)
+ arch/ppc/cpu/ppc4xx/start.o (.text)
board/xes/xpedite1000/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
+ arch/ppc/cpu/ppc4xx/kgdb.o (.text)
+ arch/ppc/cpu/ppc4xx/traps.o (.text)
+ arch/ppc/cpu/ppc4xx/interrupts.o (.text)
+ arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/ppc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
.plt : { *(.plt) }
.text :
{
- cpu/mpc86xx/start.o (.text)
- cpu/mpc86xx/traps.o (.text)
- cpu/mpc86xx/interrupts.o (.text)
- cpu/mpc86xx/cpu_init.o (.text)
- cpu/mpc86xx/cpu.o (.text)
- cpu/mpc86xx/speed.o (.text)
+ arch/ppc/cpu/mpc86xx/start.o (.text)
+ arch/ppc/cpu/mpc86xx/traps.o (.text)
+ arch/ppc/cpu/mpc86xx/interrupts.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/ppc/cpu/mpc86xx/cpu.o (.text)
+ arch/ppc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/ppc/lib/extable.o (.text)
.bootpg 0xFFFFF000 :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
.bootpg 0xFFFFF000 :
{
- cpu/ppc4xx/start.o (.bootpg)
+ arch/ppc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
# Some architecture config.mk files need to know what CPUDIR is set to,
# so calculate CPUDIR before including ARCH/SOC/CPU config.mk files.
-CPUDIR=cpu/$(CPU)
+# Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains
+# CPU-specific code.
+CPUDIR=arch/$(ARCH)/cpu/$(CPU)
+ifneq ($(SRCTREE)/$(CPUDIR),$(wildcard $(SRCTREE)/$(CPUDIR)))
+CPUDIR=arch/$(ARCH)/cpu
+endif
sinclude $(TOPDIR)/arch/$(ARCH)/config.mk # include architecture dependend rules
sinclude $(TOPDIR)/$(CPUDIR)/config.mk # include CPU specific rules
added console settings from environment
- common/devices.c added ISA keyboard init
- common/main.c corrected the read of bootdelay
-- cpu/ppc4xx/405gp_pci.c excluded file from PIP405
-- cpu/ppc4xx/i2c.c added 16bit read write I2C support
+- arch/ppc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
+- arch/ppc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
added page write
-- cpu/ppc4xx/speed.c added get_PCI_freq
-- cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
+- arch/ppc/cpu/ppc4xx/speed.c added get_PCI_freq
+- arch/ppc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
- disk/Makefile added part_iso for CD support
- disk/part.c changed to work with block device description
added ISO CD support
"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
and custom versions.
Changed files:
-- cpu/ppc4xx/start.s
+- arch/ppc/cpu/ppc4xx/start.s
Firmware Image:
---------------
Correct PCI Frequency for PPC405:
---------------------------------
-Added function (in cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
+Added function (in arch/ppc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
The PCI Frequency will now be set correct in the board description in common/board.c.
(was set to the busfreq before).
Changed files:
-- cpu/ppc4xx/speed.c
+- arch/ppc/cpu/ppc4xx/speed.c
- common/board.c
I2C Stuff:
Added 16bit read/write support for I2C (PPC405), and page write to
I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
Changed files:
-- cpu/ppc4xx/i2c.c
+- arch/ppc/cpu/ppc4xx/i2c.c
- common/cmd_i2c.c
Environment / Console:
reconfiguration of the physical interface chip.
The test routines for the SCC ethernet tests will be located in
-cpu/mpc8xx/scc.c.
+arch/ppc/cpu/mpc8xx/scc.c.
2.2.3.2. UART tests (SMC/SCC)
test will be executed manually.
The test routine for the SMC/SCC UART tests will be located in
-cpu/mpc8xx/serial.c.
+arch/ppc/cpu/mpc8xx/serial.c.
2.2.3.3. USB test
board/RPXLITE/RPXLITE.c /* DRAM-related routines */
board/RPXLITE/flash.c /* flash-related routines */
board/RPXLITE/config.mk /* set text base address */
- cpu/mpc8xx/serial.c /* board specific register setting */
+ arch/ppc/cpu/mpc8xx/serial.c /* board specific register setting */
include/config_RPXLITE.h /* board specific registers */
See 'reg_config.txt' for register values in detail.
MAKEALL - TQM8260 entry added
Makefile - TQM8260_config entry added
-cpu/mpc8260/Makefile - soft_i2c.o module added
-cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
+arch/ppc/cpu/mpc8260/Makefile - soft_i2c.o module added
+arch/ppc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
bug fixed (fcr -> scr)
-cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
+arch/ppc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
include/flash.h - added definitions for the AM29LV640D Flash chip
board/tqm8260/flash.c - flash driver (for AM29LV640D)
board/tqm8260/ppcboot.lds - linker script
board/tqm8260/tqm8260.c - ioport and memory initialization
-cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
+arch/ppc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
include/config_TQM8260.h - main configuration file
- board/alaska/config.mk config make
- board/alaska/u-boot.lds Linker description
-- cpu/mpc8220/dma.h multi-channel dma header file
-- cpu/mpc8220/dramSetup.h dram setup header file
-- cpu/mpc8220/fec.h MPC8220 FEC header file
-- cpu/mpc8220/cpu.c cpu specific code
-- cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
-- cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
-- cpu/mpc8220/fec.c MPC8220 FEC driver
-- cpu/mpc8220/i2c.c MPC8220 I2C driver
-- cpu/mpc8220/interrupts.c interrupt support (not enable)
-- cpu/mpc8220/loadtask.c load dma
-- cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
-- cpu/mpc8220/traps.c exception
-- cpu/mpc8220/uart.c MPC8220 UART driver
-- cpu/mpc8220/Makefile Makefile
-- cpu/mpc8220/config.mk config make
-- cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
-- cpu/mpc8220/io.S io functions
-- cpu/mpc8220/start.S start up
+- arch/ppc/cpu/mpc8220/dma.h multi-channel dma header file
+- arch/ppc/cpu/mpc8220/dramSetup.h dram setup header file
+- arch/ppc/cpu/mpc8220/fec.h MPC8220 FEC header file
+- arch/ppc/cpu/mpc8220/cpu.c cpu specific code
+- arch/ppc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
+- arch/ppc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
+- arch/ppc/cpu/mpc8220/fec.c MPC8220 FEC driver
+- arch/ppc/cpu/mpc8220/i2c.c MPC8220 I2C driver
+- arch/ppc/cpu/mpc8220/interrupts.c interrupt support (not enable)
+- arch/ppc/cpu/mpc8220/loadtask.c load dma
+- arch/ppc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
+- arch/ppc/cpu/mpc8220/traps.c exception
+- arch/ppc/cpu/mpc8220/uart.c MPC8220 UART driver
+- arch/ppc/cpu/mpc8220/Makefile Makefile
+- arch/ppc/cpu/mpc8220/config.mk config make
+- arch/ppc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
+- arch/ppc/cpu/mpc8220/io.S io functions
+- arch/ppc/cpu/mpc8220/start.S start up
- include/mpc8220.h
./common/board.c
Added call to initialize debugger on startup.
-./cpu/ppc4xx/Makefile
+./arch/ppc/cpu/ppc4xx/Makefile
Added bedbug_405.c to the Makefile.
-./cpu/ppc4xx/start.S
+./arch/ppc/cpu/ppc4xx/start.S
Added code to handle the debug exception (0x2000) on the 405.
Also added code to handle critical exceptions since the debug
is treated as critical on the 405.
-./cpu/ppc4xx/traps.c
+./arch/ppc/cpu/ppc4xx/traps.c
Added more detailed output for the program exception to tell
if it is an illegal instruction, privileged instruction or
a trap. Also added debug trap handler.
hardware breakpoints and stepping through code. These
routines are common to all PowerPC processors.
-./cpu/ppc4xx/bedbug_405.c
+./arch/ppc/cpu/ppc4xx/bedbug_405.c
AMCC PPC405 specific debugger routines.
common/cmd_bedbug.c
Added call to initialize 860 debugger.
- cpu/mpc8xx/Makefile
+ arch/ppc/cpu/mpc8xx/Makefile
Added new file "bedbug_860.c" to the makefile
- cpu/mpc8xx/start.S
+ arch/ppc/cpu/mpc8xx/start.S
Added handler for InstructionBreakpoint (0xfd00)
- cpu/mpc8xx/traps.c
+ arch/ppc/cpu/mpc8xx/traps.c
Added new routine DebugException()
New Files:
- cpu/mpc8xx/bedbug_860.c
+ arch/ppc/cpu/mpc8xx/bedbug_860.c
CPU-specific routines for 860 debug registers.
u-boot-0.2.0/common/cmd_boot.c
u-boot-0.2.0/common/cmd_reginfo.c
u-boot-0.2.0/common/environment.c
-u-boot-0.2.0/cpu/mpc5xx/*
+u-boot-0.2.0/arch/ppc/cpu/mpc5xx/*
u-boot-0.2.0/include/cmd_reginfo.h
u-boot-0.2.0/include/common.h
u-boot-0.2.0/include/ppc_asm.tmpl
/*--------------------------------------------------------------------+
* Fixed PHY (PHY-less) support for Ethernet Ports.
*
- * Copied from cpu/ppc4xx/4xx_enet.c
+ * Copied from arch/ppc/cpu/ppc4xx/4xx_enet.c
*--------------------------------------------------------------------*/
/*
/*
* Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
- * With help from the common/soft_spi and cpu/mpc8260 drivers
+ * With help from the common/soft_spi and arch/ppc/cpu/mpc8260 drivers
*
* See file CREDITS for list of people who contributed to this
* project.
/* The dpalloc function used and implemented in this file was derieved
- * from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c".
+ * from PPCBoot/U-Boot file "arch/ppc/cpu/mpc8260/commproc.c".
*/
/* Author: Arun Dharankar <ADharankar@ATTBI.Com>
/*
* Backward compatible definitions,
- * so we do not have to change cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c
*/
#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
#define CONFIG_SYS_FLASH_BASE 0xfe000000
/*
- * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this
+ * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this
* variable defined
*/
#define CONFIG_SYS_FLASH_SIZE 0x02000000
* SDRAM Controller DDR autocalibration values and takes a lot longer
* to run than Method_B.
* (See the Method_A and Method_B algorithm discription in the file:
- * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
*
* DDR Autocalibration Method_B is the default.
* taken from the orignal Linkstation boot code
*
* Most of the low level configuration setttings are normally used
- * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
+ * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
* Low level initialisation is done in board/linkstation/early_init.S
* The values below are included for reference purpose only
*/
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/start.S */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
* Taken from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CONFIG_SYS_EBC_PB0AP 0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
*
* Taken in part from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRH 0x55555550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
* - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
* - Stackpointer will be located to
* (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
- * in cpu/ppc4xx/start.S
+ * in arch/ppc/cpu/ppc4xx/start.S
*/
#undef CONFIG_SYS_INIT_DCACHE_CS
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* ################################################################################### */
-/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
+/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
/* This chip select accesses the boot device */
# from cpu directory
$(obj)cache.S:
@rm -f $(obj)cache.S
- ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)gpio.c:
@rm -f $(obj)gpio.c
- ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/gpio.c $(obj)gpio.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)memory.c:
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
# from cpu directory
$(obj)44x_spd_ddr2.c: $(obj)ecc.h
@rm -f $(obj)44x_spd_ddr2.c
- ln -s $(SRCTREE)/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
$(obj)cache.S:
@rm -f $(obj)cache.S
- ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)ecc.h:
@rm -f $(obj)ecc.h
- ln -s $(SRCTREE)/cpu/ppc4xx/ecc.h $(obj)ecc.h
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/ecc.h $(obj)ecc.h
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from nand_spl directory
$(obj)nand_boot.c:
# from cpu directory
$(obj)denali_data_eye.c:
@rm -f $(obj)denali_data_eye.c
- ln -s $(SRCTREE)/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)nand_init.c:
- ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
$(obj)cache.c:
ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)nand_init.c:
- ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
$(obj)cache.c:
ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
$(obj)start.S:
@rm -f $@
- ln -s $(SRCTREE)/cpu/mpc83xx/start.S $@
+ ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $@
$(obj)nand_boot_fsl_elbc.c:
@rm -f $@
$(obj)nand_init.c:
@rm -f $@
- ln -s $(SRCTREE)/cpu/mpc83xx/nand_init.c $@
+ ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $@
$(obj)cache.c:
@rm -f $@
/* Additional Special-Purpose Registers.
* The values must match the initialization
- * values from cpu/ppc4xx/start.S
+ * values from arch/ppc/cpu/ppc4xx/start.S
*/
{0x30, "PID", 0x00000000, 0x00000000},
{0x3a, "CSRR0", 0x00000000, 0x00000000},
projects / platform / kernel / u-boot.git / commitdiff