2010-09-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

	PR target/44392
	* config/arm/arm.md (bswapsi2): Handle condition correctly
	for armv6 and optimize_size.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@164029 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b909355..c121a35 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2010-09-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       PR target/44392
+       * config/arm/arm.md (bswapsi2): Handle condition correctly
+       for armv6 and optimize_size.
+
 2010-09-08  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
 
        PR other/18555

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 9d98ca5..8806dc5 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -10658,34 +10658,29 @@
 (define_expand "bswapsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
        (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
-"TARGET_EITHER"
+"TARGET_EITHER && (arm_arch6 || !optimize_size)"
 "
-  if (!arm_arch6)
-    {
-      if (!optimize_size)
-       {
-         rtx op2 = gen_reg_rtx (SImode);
-         rtx op3 = gen_reg_rtx (SImode);
+    if (!arm_arch6)
+      {
+       rtx op2 = gen_reg_rtx (SImode);
+       rtx op3 = gen_reg_rtx (SImode);
 
-         if (TARGET_THUMB)
-           {
-             rtx op4 = gen_reg_rtx (SImode);
-             rtx op5 = gen_reg_rtx (SImode);
+       if (TARGET_THUMB)
+         {
+           rtx op4 = gen_reg_rtx (SImode);
+           rtx op5 = gen_reg_rtx (SImode);
 
-             emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
-                                              op2, op3, op4, op5));
-           }
-         else
-           {
-             emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
-                                            op2, op3));
-           }
+           emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
+                                            op2, op3, op4, op5));
+         }
+       else
+         {
+           emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
+                                          op2, op3));
+         }
 
-         DONE;
-       }
-      else
-       FAIL;
-    }
+       DONE;
+      }
   "
 )