drm/amd/display: fix mapping to non-allocated address

[ Upstream commit 9190d4a263264eabf715f5fc1827da45e3fdc247 ]

[Why]
There is an issue mapping non-allocated location of memory.
It would allocate gpio registers from an array out of bounds.

[How]
Patch correct numbers of bounds for using.

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
index 9b63c6c..e0bd0c7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
@@ -138,7 +138,8 @@ static const struct ddc_sh_mask ddc_shift[] = {
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
-       DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+       DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
+       DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
 };
 
 static const struct ddc_sh_mask ddc_mask[] = {
@@ -147,7 +148,8 @@ static const struct ddc_sh_mask ddc_mask[] = {
        DDC_MASK_SH_LIST_DCN2(_MASK, 3),
        DDC_MASK_SH_LIST_DCN2(_MASK, 4),
        DDC_MASK_SH_LIST_DCN2(_MASK, 5),
-       DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+       DDC_MASK_SH_LIST_DCN2(_MASK, 6),
+       DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
 };
 
 #include "../generic_regs.h"

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
index 687d4f1..36a5736 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
@@ -145,7 +145,8 @@ static const struct ddc_sh_mask ddc_shift[] = {
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
-       DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+       DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
+       DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
 };
 
 static const struct ddc_sh_mask ddc_mask[] = {
@@ -154,7 +155,8 @@ static const struct ddc_sh_mask ddc_mask[] = {
        DDC_MASK_SH_LIST_DCN2(_MASK, 3),
        DDC_MASK_SH_LIST_DCN2(_MASK, 4),
        DDC_MASK_SH_LIST_DCN2(_MASK, 5),
-       DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+       DDC_MASK_SH_LIST_DCN2(_MASK, 6),
+       DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
 };
 
 #include "../generic_regs.h"

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
index 0ea52ba..9f6872a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
@@ -149,7 +149,8 @@ static const struct ddc_sh_mask ddc_shift[] = {
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
        DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
-       DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
+       DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
+       DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
 };
 
 static const struct ddc_sh_mask ddc_mask[] = {
@@ -158,7 +159,8 @@ static const struct ddc_sh_mask ddc_mask[] = {
        DDC_MASK_SH_LIST_DCN2(_MASK, 3),
        DDC_MASK_SH_LIST_DCN2(_MASK, 4),
        DDC_MASK_SH_LIST_DCN2(_MASK, 5),
-       DDC_MASK_SH_LIST_DCN2(_MASK, 6)
+       DDC_MASK_SH_LIST_DCN2(_MASK, 6),
+       DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
 };
 
 #include "../generic_regs.h"

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
index 308a543..59884ef 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
@@ -113,6 +113,13 @@
        (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
        (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
 
+#define DDC_MASK_SH_LIST_DCN2_VGA(mask_sh) \
+       {DDC_MASK_SH_LIST_COMMON(mask_sh),\
+       0,\
+       0,\
+       0,\
+       0}
+
 struct ddc_registers {
        struct gpio_registers gpio;
        uint32_t ddc_setup;