}
static void
+do_mve_vmaxnmv (void)
+{
+ enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ if (inst.operands[0].reg == REG_SP)
+ as_tsktsk (MVE_BAD_SP);
+ else if (inst.operands[0].reg == REG_PC)
+ as_tsktsk (MVE_BAD_PC);
+
+ mve_encode_rq (et.size == 16, 64);
+}
+
+static void
do_neon_qrdmlah (void)
{
/* Check we're on the correct architecture. */
mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
+ mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
+ mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
+ mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
+ mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vmaxnmv.f64 r0,q1'
+[^:]*:11: Error: bad type in SIMD instruction -- `vmaxnmv.i16 r0,q1'
+[^:]*:12: Error: bad type in SIMD instruction -- `vminnmv.f64 r0,q1'
+[^:]*:13: Error: bad type in SIMD instruction -- `vminnmv.i16 r0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vmaxnmav.f64 r0,q1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vmaxnmav.i16 r0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vminnmav.f64 r0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vminnmav.i16 r0,q1'
+[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
+[^:]*:28: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
+[^:]*:30: Error: syntax error -- `vmaxnmveq.f32 r0,q1'
+[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmvt.f32 r0,q1'
+[^:]*:33: Error: instruction missing MVE vector predication code -- `vmaxnmv.f32 r0,q1'
+[^:]*:35: Error: syntax error -- `vmaxnmaveq.f32 r0,q1'
+[^:]*:36: Error: syntax error -- `vmaxnmaveq.f32 r0,q1'
+[^:]*:38: Error: syntax error -- `vmaxnmaveq.f32 r0,q1'
+[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vmaxnmavt.f32 r0,q1'
+[^:]*:41: Error: instruction missing MVE vector predication code -- `vmaxnmav.f32 r0,q1'
+[^:]*:43: Error: syntax error -- `vminnmveq.f32 r0,q1'
+[^:]*:44: Error: syntax error -- `vminnmveq.f32 r0,q1'
+[^:]*:46: Error: syntax error -- `vminnmveq.f32 r0,q1'
+[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmvt.f32 r0,q1'
+[^:]*:49: Error: instruction missing MVE vector predication code -- `vminnmv.f32 r0,q1'
+[^:]*:51: Error: syntax error -- `vminnmaveq.f32 r0,q1'
+[^:]*:52: Error: syntax error -- `vminnmaveq.f32 r0,q1'
+[^:]*:54: Error: syntax error -- `vminnmaveq.f32 r0,q1'
+[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vminnmavt.f32 r0,q1'
+[^:]*:57: Error: instruction missing MVE vector predication code -- `vminnmav.f32 r0,q1'