(set (match_dup 0) (fix:DI (match_dup 2)))]
"")
+;; Avoid vector decoded form of the instruction.
+(define_peephole2
+ [(match_scratch:SF 2 "x")
+ (set (match_operand:DI 0 "register_operand" "")
+ (fix:DI (match_operand:SF 1 "memory_operand" "")))]
+ "TARGET_K8 && !optimize_size"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (fix:DI (match_dup 2)))]
+ "")
+
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
(set (match_dup 0) (fix:DI (match_dup 2)))]
"")
+;; Avoid vector decoded form of the instruction.
+(define_peephole2
+ [(match_scratch:DF 2 "Y")
+ (set (match_operand:DI 0 "register_operand" "")
+ (fix:DI (match_operand:DF 1 "memory_operand" "")))]
+ "TARGET_K8 && !optimize_size"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (fix:DI (match_dup 2)))]
+ "")
+
;; Signed conversion to SImode.
(define_expand "fix_truncxfsi2"
(set (match_dup 0) (fix:SI (match_dup 2)))]
"")
+;; Avoid vector decoded form of the instruction.
+(define_peephole2
+ [(match_scratch:SF 2 "x")
+ (set (match_operand:SI 0 "register_operand" "")
+ (fix:SI (match_operand:SF 1 "memory_operand" "")))]
+ "TARGET_K8 && !optimize_size"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (fix:SI (match_dup 2)))]
+ "")
+
(define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
(define_peephole2
[(match_scratch:DF 2 "Y")
(set (match_operand:SI 0 "register_operand" "")
+ (fix:SI (match_operand:DF 1 "memory_operand" "")))]
+ "TARGET_K8 && !optimize_size"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (fix:SI (match_dup 2)))]
+ "")
+
+;; Avoid vector decoded form of the instruction.
+(define_peephole2
+ [(match_scratch:DF 2 "Y")
+ (set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_K8 && !optimize_size"
[(set (match_dup 2) (match_dup 1))