Merge branches 'hwmod_am335x_support_3.6', 'clkdm_pwrdm_devel_a_3.6' and 'misc_devel_...

diff --cc arch/arm/mach-omap2/omap_hwmod_common_data.c
index 6dd922e,51e5418,aff6138..9f1ccdc
--- 1/arch/arm/mach-omap2/omap_hwmod_common_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_common_data.c
--- 3/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@@@ -47,17 -47,8 -47,9 +47,18 @@@@ struct omap_hwmod_sysc_fields omap_hwmo
        .midle_shift    = SYSC_TYPE2_MIDLEMODE_SHIFT,
        .sidle_shift    = SYSC_TYPE2_SIDLEMODE_SHIFT,
        .srst_shift     = SYSC_TYPE2_SOFTRESET_SHIFT,
++      .dmadisable_shift = SYSC_TYPE2_DMADISABLE_SHIFT,
 + };
 + 
 ++/**
 ++ * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
 ++ * Used by some IPs on AM33xx
 ++ */
 ++struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
 ++     .midle_shift    = SYSC_TYPE3_MIDLEMODE_SHIFT,
 ++     .sidle_shift    = SYSC_TYPE3_SIDLEMODE_SHIFT,
  +};
  +
   struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
        .manager_count          = 2,
        .has_framedonetv_irq    = 0

diff --cc arch/arm/plat-omap/include/plat/omap_hwmod.h
index 7cb8d7d,c835b71,27455ed..35675b2
--- 1/arch/arm/plat-omap/include/plat/omap_hwmod.h
--- 2/arch/arm/plat-omap/include/plat/omap_hwmod.h
--- 3/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@@@ -70,16 -69,7 -69,9 +70,18 @@@@ extern struct omap_hwmod_sysc_fields om
   #define SYSC_TYPE2_SIDLEMODE_MASK    (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
   #define SYSC_TYPE2_MIDLEMODE_SHIFT   4
   #define SYSC_TYPE2_MIDLEMODE_MASK    (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
++ #define SYSC_TYPE2_DMADISABLE_SHIFT  16
++ #define SYSC_TYPE2_DMADISABLE_MASK   (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
 + 
 ++/*
 ++ * OCP SYSCONFIG bit shifts/masks TYPE3.
 ++ * This is applicable for some IPs present in AM33XX
 ++ */
 ++#define SYSC_TYPE3_SIDLEMODE_SHIFT   0
 ++#define SYSC_TYPE3_SIDLEMODE_MASK    (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
 ++#define SYSC_TYPE3_MIDLEMODE_SHIFT   2
 ++#define SYSC_TYPE3_MIDLEMODE_MASK    (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
  +
   /* OCP SYSSTATUS bit shifts/masks */
   #define SYSS_RESETDONE_SHIFT         0
   #define SYSS_RESETDONE_MASK          (1 << SYSS_RESETDONE_SHIFT)