ARM: socfpga: dts: Add div-reg to the main_pll clocks

The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 5dfd145..f72e80e 100644 (file)
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -21,8 +21,8 @@ Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
         and the bit index.
-- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
-        and width.
+- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
+       the divider register, bit shift, and width.
 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
        the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
        value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 917464a..280966b 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -148,7 +148,7 @@
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
                                                        clocks = <&main_pll>;
-                                                       fixed-divider = <2>;
+                                                       div-reg = <0xe0 0 9>;
                                                        reg = <0x48>;
                                                };
 
@@ -156,7 +156,7 @@
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
                                                        clocks = <&main_pll>;
-                                                       fixed-divider = <4>;
+                                                       div-reg = <0xe4 0 9>;
                                                        reg = <0x4C>;
                                                };
 
@@ -164,7 +164,7 @@
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
                                                        clocks = <&main_pll>;
-                                                       fixed-divider = <4>;
+                                                       div-reg = <0xe8 0 9>;
                                                        reg = <0x50>;
                                                };