drm/amd/display: clean up DCHUBBUB register definition in hwseq

Cleanup to remove unused register definition from hw sequencer
header file since implementation moved from hw sequencer to dchubub file.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index aea6494..3336428 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -141,25 +141,7 @@
 
 #define HWSEQ_DCN_REG_LIST()\
        SR(REFCLK_CNTL), \
-       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
-       SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
-       SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
-       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
-       SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
-       SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
-       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
-       SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
-       SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
-       SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
-       SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
-       SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
-       SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
-       SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
-       SR(DCHUBBUB_ARB_SAT_LEVEL),\
-       SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
        SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
-       SR(DCHUBBUB_TEST_DEBUG_INDEX), \
-       SR(DCHUBBUB_TEST_DEBUG_DATA), \
        SR(DIO_MEM_PWR_CTRL), \
        SR(DCCG_GATE_DISABLE_CNTL), \
        SR(DCCG_GATE_DISABLE_CNTL2), \
@@ -179,22 +161,10 @@
        MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
        MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
 
-#define HWSEQ_SR_WATERMARK_REG_LIST()\
-       SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
-       SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
-
 #define HWSEQ_DCN1_REG_LIST()\
        HWSEQ_DCN_REG_LIST(), \
-       HWSEQ_SR_WATERMARK_REG_LIST(), \
        HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
        HWSEQ_PHYPLL_REG_LIST(OTG), \
-       SR(DCHUBBUB_SDPIF_FB_TOP),\
        SR(DCHUBBUB_SDPIF_FB_BASE),\
        SR(DCHUBBUB_SDPIF_FB_OFFSET),\
        SR(DCHUBBUB_SDPIF_AGP_BASE),\
@@ -245,34 +215,8 @@ struct dce_hwseq_registers {
        uint32_t DCHUB_AGP_TOP;
 
        uint32_t REFCLK_CNTL;
-       uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
-       uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
-       uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
-       uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
-       uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
-       uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
-       uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
-       uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
-       uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
-       uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
-       uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
-       uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
-       uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
-       uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
-       uint32_t DCHUBBUB_ARB_SAT_LEVEL;
-       uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
+
        uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
-       uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
-       uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
-       uint32_t DCHUBBUB_TEST_DEBUG_DATA;
-       uint32_t DCHUBBUB_SDPIF_FB_TOP;
        uint32_t DCHUBBUB_SDPIF_FB_BASE;
        uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
        uint32_t DCHUBBUB_SDPIF_AGP_BASE;
@@ -414,20 +358,11 @@ struct dce_hwseq_registers {
        HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
        HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
        HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
-       HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
        HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
 
 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
        HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
        HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
-       HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
        HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
        HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
        HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
@@ -507,7 +442,6 @@ struct dce_hwseq_registers {
        type HUBP_VTG_SEL; \
        type HUBP_CLOCK_ENABLE; \
        type DPP_CLOCK_ENABLE; \
-       type SDPIF_FB_TOP;\
        type SDPIF_FB_BASE;\
        type SDPIF_FB_OFFSET;\
        type SDPIF_AGP_BASE;\
@@ -520,14 +454,6 @@ struct dce_hwseq_registers {
        type AGP_BOT;\
        type AGP_TOP;\
        type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
-       type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
-       type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
-       type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
-       type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
-       type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
-       type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
-       type DCHUBBUB_ARB_SAT_LEVEL;\
-       type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
        type OPP_PIPE_CLOCK_EN;\
        type IP_REQUEST_EN; \
        type DOMAIN0_POWER_FORCEON; \