case MVT::i1: {
// The only legal i1 vectors are SVE vectors, so we can use SVE-specific
// lowering code.
- if (auto *ConstVal = dyn_cast<ConstantSDNode>(SplatVal)) {
- // We can hande the zero case during isel.
- if (ConstVal->isZero())
- return Op;
- if (ConstVal->isOne())
- return getPTrue(DAG, dl, VT, AArch64SVEPredPattern::all);
- }
+
+ // We can handle the constant cases during isel.
+ if (isa<ConstantSDNode>(SplatVal))
+ return Op;
+
// The general case of i1. There isn't any natural way to do this,
// so we use some trickery with whilelo.
SplatVal = DAG.getAnyExtOrTrunc(SplatVal, dl, MVT::i64);
return false;
}
+ if (ISD::isConstantSplatVectorAllOnes(N.getNode()))
+ return true;
+
// "ptrue p.<ty>, all" can be considered all active when <ty> is the same size
// or smaller than the implicit element type represented by N.
// NOTE: A larger element count implies a smaller element type.
let Predicates = [HasSVEorStreamingSVE] in {
defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
defm PTRUES : sve_int_ptrue<0b001, "ptrues", null_frag>;
+
+ def : Pat<(nxv16i1 immAllOnesV), (PTRUE_B 31)>;
+ def : Pat<(nxv8i1 immAllOnesV), (PTRUE_H 31)>;
+ def : Pat<(nxv4i1 immAllOnesV), (PTRUE_S 31)>;
+ def : Pat<(nxv2i1 immAllOnesV), (PTRUE_D 31)>;
}
//===----------------------------------------------------------------------===//
multiclass sve_int_pfalse<bits<6> opc, string asm> {
def NAME : sve_int_pfalse<opc, asm>;
- def : Pat<(nxv16i1 (splat_vector (i32 0))), (!cast<Instruction>(NAME))>;
- def : Pat<(nxv8i1 (splat_vector (i32 0))), (!cast<Instruction>(NAME))>;
- def : Pat<(nxv4i1 (splat_vector (i32 0))), (!cast<Instruction>(NAME))>;
- def : Pat<(nxv2i1 (splat_vector (i32 0))), (!cast<Instruction>(NAME))>;
+ def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>;
+ def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>;
+ def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>;
+ def : Pat<(nxv2i1 immAllZerosV), (!cast<Instruction>(NAME))>;
}
class sve_int_ptest<bits<6> opc, string asm>