Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and...

 - Support custom flags in Xilinx zynq firmware
 - Various small fixes to the Xilinx clk driver
 - Support for Intel Agilex clks

* clk-tegra:
  clk: tegra: Add Tegra210 CSI TPG clock gate
  clk: tegra30: Use custom CCLK implementation
  clk: tegra20: Use custom CCLK implementation
  clk: tegra: cclk: Add helpers for handling PLLX rate changes
  clk: tegra: pll: Add pre/post rate-change hooks
  clk: tegra: Add custom CCLK implementation
  clk: tegra: Remove the old emc_mux clock for Tegra210
  clk: tegra: Implement Tegra210 EMC clock
  clk: tegra: Export functions for EMC clock scaling
  clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
  clk: tegra: Rename Tegra124 EMC clock source file
  dt-bindings: clock: tegra: Add clock ID for CSI TPG clock

* clk-imx:
  clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
  clk: imx: add imx8m_clk_hw_composite_bus
  clk: imx: add mux ops for i.MX8M composite clk
  clk: imx8m: migrate A53 clk root to use composite core
  clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
  clk: imx8mp: Define gates for pll1/2 fixed dividers
  clk: imx: imx8mp: fix pll mux bit
  clk: imx8m: drop clk_hw_set_parent for A53
  dt-bindings: clocks: imx8mp: Add ids for audiomix clocks
  clk: imx: Add helpers for passing the device as argument
  clk: imx: pll14xx: Add the device as argument when registering
  clk: imx: gate2: Allow single bit gating clock
  clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait
  clk: imx: clk-sscg-pll: Remove unnecessary blank lines
  clk: imx: drop the dependency on ARM64 for i.MX8M
  clk: imx7ulp: make it easy to change ARM core clk
  clk: imx: imx6ul: change flexcan clock to support CiA bitrates

* clk-zynq:
  clk: zynqmp: Make zynqmp_clk_get_max_divisor static
  clk: zynqmp: Update fraction clock check from custom type flags
  clk: zynqmp: Add support for custom type flags
  clk: zynqmp: fix memory leak in zynqmp_register_clocks
  clk: zynqmp: Fix invalid clock name queries
  clk: zynqmp: Fix divider2 calculation
  clk: zynqmp: Limit bestdiv with maxdiv

* clk-socfpga:
  clk: socfpga: agilex: add clock driver for the Agilex platform
  dt-bindings: documentation: add clock bindings information for Agilex
  clk: socfpga: add const to _ops data structures
  clk: socfpga: remove clk_ops enable/disable methods
  clk: socfpga: stratix10: use new parent data scheme

* clk-at91:
  clk: at91: allow setting all PMC clock parents via DT
  clk: at91: allow setting PCKx parent via DT
  clk: at91: optimize pmc data allocation
  clk: at91: pmc: decrement node's refcount
  clk: at91: pmc: do not continue if compatible not located
  clk: at91: Add peripheral clock for PTC

* clk-ti:
  clk: ti: dra7: remove two unused symbols
  clk: ti: dra7xx: fix RNG clock parent
  clk: ti: dra7xx: mark MCAN clock as DRA76x only
  clk: ti: dra7xx: fix gpu clkctrl parent
  clk: ti: omap5: Add proper parent clocks for l4-secure clocks
  clk: ti: omap4: Add proper parent clocks for l4-secure clocks
  clk: ti: composite: fix memory leak