[SLP] Simplify extendSchedulingRegion

This change uses instruction's comesBefore method to simplify the code significantly. There's little compile time concern here because getSpillCost already calls comesBefore on every basic block which contains a vectorization candidate. The only additional times we'll build basic block ordering is when we can't schedule a vector candidate anywhere in the containing block.

Differential Revision: https://reviews.llvm.org/D120364

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 3e87b3b..9b38be0 100644 (file)
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -7621,21 +7621,8 @@ BoUpSLP::BlockScheduling::extendSchedulingRegion(Value *V,
     LLVM_DEBUG(dbgs() << "SLP:  initialize schedule region to " << *I << "\n");
     return;
   }
-  // Search up and down at the same time, because we don't know if the new
-  // instruction is above or below the existing scheduling region.
-  BasicBlock::reverse_iterator UpIter =
-      ++ScheduleStart->getIterator().getReverse();
-  BasicBlock::reverse_iterator UpperEnd = BB->rend();
-  BasicBlock::iterator DownIter = ScheduleEnd->getIterator();
-  BasicBlock::iterator LowerEnd = BB->end();
-  while (UpIter != UpperEnd && DownIter != LowerEnd && &*UpIter != I &&
-         &*DownIter != I) {
-    ++UpIter;
-    ++DownIter;
-  }
-  if (DownIter == LowerEnd || (UpIter != UpperEnd && &*UpIter == I)) {
-    assert(I->getParent() == ScheduleStart->getParent() &&
-           "Instruction is in wrong basic block.");
+
+  if (I->comesBefore(ScheduleStart)) {
     initScheduleData(I, ScheduleStart, nullptr, FirstLoadStoreInRegion);
     ScheduleStart = I;
     if (isOneOf(S, I) != I)
@@ -7644,17 +7631,14 @@ BoUpSLP::BlockScheduling::extendSchedulingRegion(Value *V,
                       << "\n");
     return;
   }
-  assert((UpIter == UpperEnd || (DownIter != LowerEnd && &*DownIter == I)) &&
-         "Expected to reach top of the basic block or instruction down the "
-         "lower end.");
-  assert(I->getParent() == ScheduleEnd->getParent() &&
-         "Instruction is in wrong basic block.");
-  initScheduleData(ScheduleEnd, I->getNextNode(), LastLoadStoreInRegion,
-                   nullptr);
-  ScheduleEnd = I->getNextNode();
+
+  auto *NextI = I->getNextNode();
+  assert(NextI && "tried to vectorize a terminator?");
+  assert(ScheduleEnd->comesBefore(NextI) && "must extend?");
+  initScheduleData(ScheduleEnd, NextI, LastLoadStoreInRegion, nullptr);
+  ScheduleEnd = NextI;
   if (isOneOf(S, I) != I)
     CheckSheduleForI(I);
-  assert(ScheduleEnd && "tried to vectorize a terminator?");
   LLVM_DEBUG(dbgs() << "SLP:  extend schedule region end to " << *I << "\n");
   return;
 }