[RISCV] Fix UBSan failure on signed integer overflow.
authorCraig Topper <craig.topper@sifive.com>
Wed, 7 Jun 2023 01:27:33 +0000 (18:27 -0700)
committerCraig Topper <craig.topper@sifive.com>
Wed, 7 Jun 2023 01:27:33 +0000 (18:27 -0700)
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp

index 6bd30b2..27269be 100644 (file)
@@ -211,7 +211,7 @@ static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
   // constant pool.
   if (Seq.size() > 3) {
     int64_t LoVal = SignExtend64<32>(Imm);
-    int64_t HiVal = SignExtend64<32>((Imm - LoVal) >> 32);
+    int64_t HiVal = SignExtend64<32>(((uint64_t)Imm - (uint64_t)LoVal) >> 32);
     if (LoVal == HiVal) {
       RISCVMatInt::InstSeq SeqLo =
           RISCVMatInt::generateInstSeq(LoVal, Subtarget.getFeatureBits());
index 90f953d..a756689 100644 (file)
@@ -4404,7 +4404,7 @@ static SDValue lowerConstant(SDValue Op, SelectionDAG &DAG,
   // that if it will avoid a constant pool.
   // It will require an extra temporary register though.
   int64_t LoVal = SignExtend64<32>(Imm);
-  int64_t HiVal = SignExtend64<32>((Imm - LoVal) >> 32);
+  int64_t HiVal = SignExtend64<32>(((uint64_t)Imm - (uint64_t)LoVal) >> 32);
   if (LoVal == HiVal) {
     RISCVMatInt::InstSeq SeqLo =
         RISCVMatInt::generateInstSeq(LoVal, Subtarget.getFeatureBits());