[Mips] Convert some tests to opaque pointers (NFC)

I'm not sure why, but the absence of bitcasts / no-op GEPs causes
the branch delay slot to be used.

Differential Revision: https://reviews.llvm.org/D141593

diff --git a/llvm/test/CodeGen/Mips/cconv/return-struct.ll b/llvm/test/CodeGen/Mips/cconv/return-struct.ll
index 49964d6..67c5827 100644 (file)
--- a/llvm/test/CodeGen/Mips/cconv/return-struct.ll
+++ b/llvm/test/CodeGen/Mips/cconv/return-struct.ll
@@ -27,7 +27,7 @@
 @struct_6xi32 = global {[6 x i32]} zeroinitializer
 @struct_128xi16 = global {[128 x i16]} zeroinitializer
 
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1)
+declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1)
 
 define inreg {i8} @ret_struct_i8() nounwind {
 ; O32-LABEL: ret_struct_i8:
@@ -70,7 +70,7 @@ define inreg {i8} @ret_struct_i8() nounwind {
 ; N64-LE-NEXT:    jr $ra
 ; N64-LE-NEXT:    lb $2, %lo(struct_byte)($1)
 entry:
-        %0 = load volatile {i8}, {i8}* @struct_byte
+        %0 = load volatile {i8}, ptr @struct_byte
         ret {i8} %0
 }
 
@@ -140,11 +140,9 @@ define inreg {i16} @ret_struct_i16() nounwind {
 ; N64-LE-NEXT:    daddiu $sp, $sp, 16
 entry:
         %retval = alloca {i8,i8}, align 1
-        %0 = bitcast {i8,i8}* %retval to i8*
-        call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds ({i8,i8}, {i8,i8}* @struct_2byte, i32 0, i32 0), i64 2, i1 false)
-        %1 = bitcast {i8,i8}* %retval to {i16}*
-        %2 = load volatile {i16}, {i16}* %1
-        ret {i16} %2
+        call void @llvm.memcpy.p0.p0.i64(ptr %retval, ptr @struct_2byte, i64 2, i1 false)
+        %0 = load volatile {i16}, ptr %retval
+        ret {i16} %0
 }
 
 ; Ensure that structures bigger than 32-bits but smaller than 64-bits are
@@ -167,9 +165,8 @@ define inreg {i48} @ret_struct_3xi16() nounwind {
 ; O32-LE-NEXT:    lui $1, %hi(struct_3xi16)
 ; O32-LE-NEXT:    lw $2, %lo(struct_3xi16)($1)
 ; O32-LE-NEXT:    addiu $1, $1, %lo(struct_3xi16)
-; O32-LE-NEXT:    lhu $3, 4($1)
 ; O32-LE-NEXT:    jr $ra
-; O32-LE-NEXT:    nop
+; O32-LE-NEXT:    lhu $3, 4($1)
 ;
 ; N32-BE-LABEL: ret_struct_3xi16:
 ; N32-BE:       # %bb.0: # %entry
@@ -221,14 +218,14 @@ define inreg {i48} @ret_struct_3xi16() nounwind {
 ; N64-LE-NEXT:    jr $ra
 ; N64-LE-NEXT:    or $2, $2, $1
 entry:
-        %0 = load volatile i48, i48* bitcast ({[3 x i16]}* @struct_3xi16 to i48*), align 2
+        %0 = load volatile i48, ptr @struct_3xi16, align 2
         %1 = insertvalue {i48} undef, i48 %0, 0
         ret {i48} %1
 }
 
 ; Ensure that large structures (>128-bit) are returned indirectly.
 ; We pick an extremely large structure so we don't have to match inlined memcpy's.
-define void @ret_struct_128xi16({[128 x i16]}* sret({[128 x i16]}) %returnval) {
+define void @ret_struct_128xi16(ptr sret({[128 x i16]}) %returnval) {
 ; O32-LABEL: ret_struct_128xi16:
 ; O32:       # %bb.0: # %entry
 ; O32-NEXT:    addiu $sp, $sp, -24
@@ -290,8 +287,7 @@ define void @ret_struct_128xi16({[128 x i16]}* sret({[128 x i16]}) %returnval) {
 ; N64-NEXT:    jr $ra
 ; N64-NEXT:    daddiu $sp, $sp, 16
 entry:
-        %0 = bitcast {[128 x i16]}* %returnval to i8*
-        call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 %0, i8* align 2 bitcast ({[128 x i16]}* @struct_128xi16 to i8*), i64 256, i1 false)
+        call void @llvm.memcpy.p0.p0.i64(ptr align 2 %returnval, ptr align 2 @struct_128xi16, i64 256, i1 false)
         ret void
 }
 
@@ -359,6 +355,6 @@ define {[6 x i32]} @ret_struct_6xi32() {
 ; N64-NEXT:    jr $ra
 ; N64-NEXT:    sw $2, 0($4)
 entry:
-        %0 = load volatile {[6 x i32]}, {[6 x i32]}* @struct_6xi32, align 2
+        %0 = load volatile {[6 x i32]}, ptr @struct_6xi32, align 2
         ret {[6 x i32]} %0
 }

diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll
index 3eb5053..3c31103 100644 (file)
--- a/llvm/test/CodeGen/Mips/load-store-left-right.ll
+++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll
@@ -30,9 +30,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS32-EL-NEXT:    addu $1, $2, $25
 ; MIPS32-EL-NEXT:    lw $1, %got(si)($1)
 ; MIPS32-EL-NEXT:    lwl $2, 3($1)
-; MIPS32-EL-NEXT:    lwr $2, 0($1)
 ; MIPS32-EL-NEXT:    jr $ra
-; MIPS32-EL-NEXT:    nop
+; MIPS32-EL-NEXT:    lwr $2, 0($1)
 ;
 ; MIPS32-EB-LABEL: load_SI:
 ; MIPS32-EB:       # %bb.0: # %entry
@@ -41,9 +40,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS32-EB-NEXT:    addu $1, $2, $25
 ; MIPS32-EB-NEXT:    lw $1, %got(si)($1)
 ; MIPS32-EB-NEXT:    lwl $2, 0($1)
-; MIPS32-EB-NEXT:    lwr $2, 3($1)
 ; MIPS32-EB-NEXT:    jr $ra
-; MIPS32-EB-NEXT:    nop
+; MIPS32-EB-NEXT:    lwr $2, 3($1)
 ;
 ; MIPS32R6-LABEL: load_SI:
 ; MIPS32R6:       # %bb.0: # %entry
@@ -51,8 +49,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(si)($1)
+; MIPS32R6-NEXT:    jr $ra
 ; MIPS32R6-NEXT:    lw $2, 0($1)
-; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS64-EL-LABEL: load_SI:
 ; MIPS64-EL:       # %bb.0: # %entry
@@ -61,9 +59,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS64-EL-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI)))
 ; MIPS64-EL-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64-EL-NEXT:    lwl $2, 3($1)
-; MIPS64-EL-NEXT:    lwr $2, 0($1)
 ; MIPS64-EL-NEXT:    jr $ra
-; MIPS64-EL-NEXT:    nop
+; MIPS64-EL-NEXT:    lwr $2, 0($1)
 ;
 ; MIPS64-EB-LABEL: load_SI:
 ; MIPS64-EB:       # %bb.0: # %entry
@@ -72,9 +69,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS64-EB-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI)))
 ; MIPS64-EB-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64-EB-NEXT:    lwl $2, 0($1)
-; MIPS64-EB-NEXT:    lwr $2, 3($1)
 ; MIPS64-EB-NEXT:    jr $ra
-; MIPS64-EB-NEXT:    nop
+; MIPS64-EB-NEXT:    lwr $2, 3($1)
 ;
 ; MIPS64R2-EL-LABEL: load_SI:
 ; MIPS64R2-EL:       # %bb.0: # %entry
@@ -83,9 +79,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS64R2-EL-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI)))
 ; MIPS64R2-EL-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64R2-EL-NEXT:    lwl $2, 3($1)
-; MIPS64R2-EL-NEXT:    lwr $2, 0($1)
 ; MIPS64R2-EL-NEXT:    jr $ra
-; MIPS64R2-EL-NEXT:    nop
+; MIPS64R2-EL-NEXT:    lwr $2, 0($1)
 ;
 ; MIPS64R2-EB-LABEL: load_SI:
 ; MIPS64R2-EB:       # %bb.0: # %entry
@@ -94,9 +89,8 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS64R2-EB-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI)))
 ; MIPS64R2-EB-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64R2-EB-NEXT:    lwl $2, 0($1)
-; MIPS64R2-EB-NEXT:    lwr $2, 3($1)
 ; MIPS64R2-EB-NEXT:    jr $ra
-; MIPS64R2-EB-NEXT:    nop
+; MIPS64R2-EB-NEXT:    lwr $2, 3($1)
 ;
 ; MIPS64R6-LABEL: load_SI:
 ; MIPS64R6:       # %bb.0: # %entry
@@ -104,10 +98,10 @@ define i32 @load_SI() nounwind readonly {
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(si)($1)
+; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    lw $2, 0($1)
-; MIPS64R6-NEXT:    jrc $ra
 entry:
-  %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1
+  %0 = load i32, ptr @si, align 1
   ret i32 %0
 }
 
@@ -190,7 +184,7 @@ define void @store_SI(i32 signext %a) nounwind {
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    sw $4, 0($1)
 entry:
-  store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1
+  store i32 %a, ptr @si, align 1
   ret void
 }
 
@@ -204,9 +198,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS32-EL-NEXT:    lwl $2, 3($1)
 ; MIPS32-EL-NEXT:    lwr $2, 0($1)
 ; MIPS32-EL-NEXT:    lwl $3, 7($1)
-; MIPS32-EL-NEXT:    lwr $3, 4($1)
 ; MIPS32-EL-NEXT:    jr $ra
-; MIPS32-EL-NEXT:    nop
+; MIPS32-EL-NEXT:    lwr $3, 4($1)
 ;
 ; MIPS32-EB-LABEL: load_SLL:
 ; MIPS32-EB:       # %bb.0: # %entry
@@ -217,9 +210,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS32-EB-NEXT:    lwl $2, 0($1)
 ; MIPS32-EB-NEXT:    lwr $2, 3($1)
 ; MIPS32-EB-NEXT:    lwl $3, 4($1)
-; MIPS32-EB-NEXT:    lwr $3, 7($1)
 ; MIPS32-EB-NEXT:    jr $ra
-; MIPS32-EB-NEXT:    nop
+; MIPS32-EB-NEXT:    lwr $3, 7($1)
 ;
 ; MIPS32R6-LABEL: load_SLL:
 ; MIPS32R6:       # %bb.0: # %entry
@@ -228,8 +220,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(sll)($1)
 ; MIPS32R6-NEXT:    lw $2, 0($1)
+; MIPS32R6-NEXT:    jr $ra
 ; MIPS32R6-NEXT:    lw $3, 4($1)
-; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS64-EL-LABEL: load_SLL:
 ; MIPS64-EL:       # %bb.0: # %entry
@@ -238,9 +230,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS64-EL-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SLL)))
 ; MIPS64-EL-NEXT:    ld $1, %got_disp(sll)($1)
 ; MIPS64-EL-NEXT:    ldl $2, 7($1)
-; MIPS64-EL-NEXT:    ldr $2, 0($1)
 ; MIPS64-EL-NEXT:    jr $ra
-; MIPS64-EL-NEXT:    nop
+; MIPS64-EL-NEXT:    ldr $2, 0($1)
 ;
 ; MIPS64-EB-LABEL: load_SLL:
 ; MIPS64-EB:       # %bb.0: # %entry
@@ -249,9 +240,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS64-EB-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SLL)))
 ; MIPS64-EB-NEXT:    ld $1, %got_disp(sll)($1)
 ; MIPS64-EB-NEXT:    ldl $2, 0($1)
-; MIPS64-EB-NEXT:    ldr $2, 7($1)
 ; MIPS64-EB-NEXT:    jr $ra
-; MIPS64-EB-NEXT:    nop
+; MIPS64-EB-NEXT:    ldr $2, 7($1)
 ;
 ; MIPS64R2-EL-LABEL: load_SLL:
 ; MIPS64R2-EL:       # %bb.0: # %entry
@@ -260,9 +250,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS64R2-EL-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SLL)))
 ; MIPS64R2-EL-NEXT:    ld $1, %got_disp(sll)($1)
 ; MIPS64R2-EL-NEXT:    ldl $2, 7($1)
-; MIPS64R2-EL-NEXT:    ldr $2, 0($1)
 ; MIPS64R2-EL-NEXT:    jr $ra
-; MIPS64R2-EL-NEXT:    nop
+; MIPS64R2-EL-NEXT:    ldr $2, 0($1)
 ;
 ; MIPS64R2-EB-LABEL: load_SLL:
 ; MIPS64R2-EB:       # %bb.0: # %entry
@@ -271,9 +260,8 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS64R2-EB-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SLL)))
 ; MIPS64R2-EB-NEXT:    ld $1, %got_disp(sll)($1)
 ; MIPS64R2-EB-NEXT:    ldl $2, 0($1)
-; MIPS64R2-EB-NEXT:    ldr $2, 7($1)
 ; MIPS64R2-EB-NEXT:    jr $ra
-; MIPS64R2-EB-NEXT:    nop
+; MIPS64R2-EB-NEXT:    ldr $2, 7($1)
 ;
 ; MIPS64R6-LABEL: load_SLL:
 ; MIPS64R6:       # %bb.0: # %entry
@@ -281,10 +269,10 @@ define i64 @load_SLL() nounwind readonly {
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SLL)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(sll)($1)
+; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    ld $2, 0($1)
-; MIPS64R6-NEXT:    jrc $ra
 entry:
-  %0 = load i64, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
+  %0 = load i64, ptr @sll, align 1
   ret i64 %0
 }
 
@@ -338,9 +326,8 @@ define i64 @load_SI_sext_to_i64() nounwind readonly {
 ; MIPS64-EL-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI_sext_to_i64)))
 ; MIPS64-EL-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64-EL-NEXT:    lwl $2, 3($1)
-; MIPS64-EL-NEXT:    lwr $2, 0($1)
 ; MIPS64-EL-NEXT:    jr $ra
-; MIPS64-EL-NEXT:    nop
+; MIPS64-EL-NEXT:    lwr $2, 0($1)
 ;
 ; MIPS64-EB-LABEL: load_SI_sext_to_i64:
 ; MIPS64-EB:       # %bb.0: # %entry
@@ -349,9 +336,8 @@ define i64 @load_SI_sext_to_i64() nounwind readonly {
 ; MIPS64-EB-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI_sext_to_i64)))
 ; MIPS64-EB-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64-EB-NEXT:    lwl $2, 0($1)
-; MIPS64-EB-NEXT:    lwr $2, 3($1)
 ; MIPS64-EB-NEXT:    jr $ra
-; MIPS64-EB-NEXT:    nop
+; MIPS64-EB-NEXT:    lwr $2, 3($1)
 ;
 ; MIPS64R2-EL-LABEL: load_SI_sext_to_i64:
 ; MIPS64R2-EL:       # %bb.0: # %entry
@@ -360,9 +346,8 @@ define i64 @load_SI_sext_to_i64() nounwind readonly {
 ; MIPS64R2-EL-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI_sext_to_i64)))
 ; MIPS64R2-EL-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64R2-EL-NEXT:    lwl $2, 3($1)
-; MIPS64R2-EL-NEXT:    lwr $2, 0($1)
 ; MIPS64R2-EL-NEXT:    jr $ra
-; MIPS64R2-EL-NEXT:    nop
+; MIPS64R2-EL-NEXT:    lwr $2, 0($1)
 ;
 ; MIPS64R2-EB-LABEL: load_SI_sext_to_i64:
 ; MIPS64R2-EB:       # %bb.0: # %entry
@@ -371,9 +356,8 @@ define i64 @load_SI_sext_to_i64() nounwind readonly {
 ; MIPS64R2-EB-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI_sext_to_i64)))
 ; MIPS64R2-EB-NEXT:    ld $1, %got_disp(si)($1)
 ; MIPS64R2-EB-NEXT:    lwl $2, 0($1)
-; MIPS64R2-EB-NEXT:    lwr $2, 3($1)
 ; MIPS64R2-EB-NEXT:    jr $ra
-; MIPS64R2-EB-NEXT:    nop
+; MIPS64R2-EB-NEXT:    lwr $2, 3($1)
 ;
 ; MIPS64R6-LABEL: load_SI_sext_to_i64:
 ; MIPS64R6:       # %bb.0: # %entry
@@ -381,10 +365,10 @@ define i64 @load_SI_sext_to_i64() nounwind readonly {
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_SI_sext_to_i64)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(si)($1)
+; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    lw $2, 0($1)
-; MIPS64R6-NEXT:    jrc $ra
 entry:
-  %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1
+  %0 = load i32, ptr @si, align 1
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
@@ -488,10 +472,10 @@ define i64 @load_UI() nounwind readonly {
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(load_UI)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(sui)($1)
+; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    lwu $2, 0($1)
-; MIPS64R6-NEXT:    jrc $ra
 entry:
-  %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1
+  %0 = load i32, ptr @sui, align 1
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
@@ -580,7 +564,7 @@ define void @store_SLL(i64 %a) nounwind {
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    sd $4, 0($1)
 entry:
-  store i64 %a, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
+  store i64 %a, ptr @sll, align 1
   ret void
 }
 
@@ -663,7 +647,7 @@ define void @store_SI_trunc_from_i64(i32 signext %a) nounwind {
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    sw $4, 0($1)
 entry:
-  store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1
+  store i32 %a, ptr @si, align 1
   ret void
 }
 
@@ -724,8 +708,8 @@ define void @copy_struct_S0() nounwind {
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    sh $2, 2($1)
 entry:
-  %0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1
-  store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1
+  %0 = load %struct.S0, ptr @struct_s0, align 1
+  store %struct.S0 %0, ptr getelementptr inbounds (%struct.S0, ptr @struct_s0, i32 1), align 1
   ret void
 }
 
@@ -822,8 +806,8 @@ define void @copy_struct_S1() nounwind {
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    sw $2, 4($1)
 entry:
-  %0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1
-  store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1
+  %0 = load %struct.S1, ptr @struct_s1, align 1
+  store %struct.S1 %0, ptr getelementptr inbounds (%struct.S1, ptr @struct_s1, i32 1), align 1
   ret void
 }
 
@@ -930,8 +914,8 @@ define void @copy_struct_S2() nounwind {
 ; MIPS64R6-NEXT:    jr $ra
 ; MIPS64R6-NEXT:    sd $2, 8($1)
 entry:
-  %0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1
-  store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1
+  %0 = load %struct.S2, ptr @struct_s2, align 1
+  store %struct.S2 %0, ptr getelementptr inbounds (%struct.S2, ptr @struct_s2, i32 1), align 1
   ret void
 }
 
@@ -1161,8 +1145,8 @@ define void @pass_array_byval() nounwind {
 ; MIPS64R2-EB-NEXT:    jr $ra
 ; MIPS64R2-EB-NEXT:    daddiu $sp, $sp, 16
 entry:
-  tail call void @extern_func([7 x i8]* byval([7 x i8]) @arr) nounwind
+  tail call void @extern_func(ptr byval([7 x i8]) @arr) nounwind
   ret void
 }
 
-declare void @extern_func([7 x i8]* byval([7 x i8]))
+declare void @extern_func(ptr byval([7 x i8]))