net: axienet: Move reset before 64-bit DMA detection

[ Upstream commit f1bc9fc4a06de0108e0dca2a9a7e99ba1fc632f9 ]

64-bit DMA detection will fail if axienet was started before (by boot
loader, boot ROM, etc). In this state axienet will not start properly.
XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to detect
64-bit DMA capability here. But datasheet says: When DMACR.RS is 1
(axienet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
is used to fetch the first descriptor. So iowrite32()/ioread32() trick
to this register to detect 64-bit DMA will not work.
So move axienet reset before 64-bit DMA detection.

Fixes: f735c40ed93c ("net: axienet: Autodetect 64-bit DMA capability")
Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
Reviewed-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/20230622192245.116864-1-fido_max@inbox.ru
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index d1d7725..d146485 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2043,6 +2043,11 @@ static int axienet_probe(struct platform_device *pdev)
                goto cleanup_clk;
        }
 
+       /* Reset core now that clocks are enabled, prior to accessing MDIO */
+       ret = __axienet_device_reset(lp);
+       if (ret)
+               goto cleanup_clk;
+
        /* Autodetect the need for 64-bit DMA pointers.
         * When the IP is configured for a bus width bigger than 32 bits,
         * writing the MSB registers is mandatory, even if they are all 0.
@@ -2097,11 +2102,6 @@ static int axienet_probe(struct platform_device *pdev)
        lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
        lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
 
-       /* Reset core now that clocks are enabled, prior to accessing MDIO */
-       ret = __axienet_device_reset(lp);
-       if (ret)
-               goto cleanup_clk;
-
        ret = axienet_mdio_setup(lp);
        if (ret)
                dev_warn(&pdev->dev,