2019-05-16 Richard Biener <rguenther@suse.de>
PR testsuite/90502
* gcc.dg/tree-ssa/vector-6.c: Adjust for half of the
transforms happening earlier now.
From-SVN: r271283
+2019-05-16 Richard Biener <rguenther@suse.de>
+
+ PR testsuite/90502
+ * gcc.dg/tree-ssa/vector-6.c: Adjust for half of the
+ transforms happening earlier now.
+
2019-05-16 Iain Sandoe <iain@sandoe.co.uk>
* lib/target-supports.exp (check_effective_target_cet): Add the
/* { dg-do compile } */
-/* { dg-options "-O -fdump-tree-ccp1 -Wno-psabi -w" } */
+/* { dg-options "-O -fdump-tree-ssa -fdump-tree-ccp1 -Wno-psabi -w" } */
/* { dg-additional-options "-msse2" { target i?86-*-* x86_64-*-* } } */
/* { dg-additional-options "-maltivec" { target powerpc_altivec_ok } } */
return v;
}
-/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 4 "ccp1" { target { { i?86-*-* x86_64-*-* aarch64*-*-* spu*-*-* } || { powerpc_altivec_ok } } } } } */
+/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 2 "ssa" { target { { i?86-*-* x86_64-*-* aarch64*-*-* spu*-*-* } || { powerpc_altivec_ok } } } } } */
+/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 2 "ccp1" { target { { i?86-*-* x86_64-*-* aarch64*-*-* spu*-*-* } || { powerpc_altivec_ok } } } } } */