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staging: rts5208: spi.c: Alignment fixes
authorWayne Porter <wporter82@gmail.com>
Tue, 11 Oct 2016 21:56:18 +0000 (21:56 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 16 Oct 2016 08:26:35 +0000 (10:26 +0200)
Lining up code with open parantheses found by checkpatch

Signed-off-by: Wayne Porter <wporter82@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/staging/rts5208/spi.c patch | blob | history

diff --git a/drivers/staging/rts5208/spi.c b/drivers/staging/rts5208/spi.c
index 5ebcdce..8b8cd95 100644 (file)
--- a/drivers/staging/rts5208/spi.c
+++ b/drivers/staging/rts5208/spi.c
@@ -117,9 +117,9 @@ static int sf_polling_status(struct rtsx_chip *chip, int msec)
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_POLLING_MODE0);
+                    SPI_TRANSFER0_START | SPI_POLLING_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, msec);
        if (retval < 0) {
@@ -144,11 +144,11 @@ static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_C_MODE0);
+                    SPI_TRANSFER0_START | SPI_C_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -173,11 +173,11 @@ static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_C_MODE0);
+                    SPI_TRANSFER0_START | SPI_C_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -191,27 +191,27 @@ static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
 }
 
 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
-               u16 len)
+                      u16 len)
 {
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
        if (addr_mode) {
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
-                       (u8)(addr >> 8));
+                            (u8)(addr >> 8));
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
-                       (u8)(addr >> 16));
+                            (u8)(addr >> 16));
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                       SPI_TRANSFER0_START | SPI_CADO_MODE0);
+                            SPI_TRANSFER0_START | SPI_CADO_MODE0);
        } else {
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                       SPI_TRANSFER0_START | SPI_CDO_MODE0);
+                            SPI_TRANSFER0_START | SPI_CDO_MODE0);
        }
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 }
 
 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
@@ -222,21 +222,21 @@ static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
        if (addr_mode) {
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
-                       (u8)(addr >> 8));
+                            (u8)(addr >> 8));
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
-                       (u8)(addr >> 16));
+                            (u8)(addr >> 16));
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                       SPI_TRANSFER0_START | SPI_CA_MODE0);
+                            SPI_TRANSFER0_START | SPI_CA_MODE0);
        } else {
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                       SPI_TRANSFER0_START | SPI_C_MODE0);
+                            SPI_TRANSFER0_START | SPI_C_MODE0);
        }
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -322,9 +322,9 @@ static int spi_eeprom_program_enable(struct rtsx_chip *chip)
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_CA_MODE0);
+                    SPI_TRANSFER0_START | SPI_CA_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -358,9 +358,9 @@ int spi_erase_eeprom_chip(struct rtsx_chip *chip)
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_CA_MODE0);
+                    SPI_TRANSFER0_START | SPI_CA_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -402,9 +402,9 @@ int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_CA_MODE0);
+                    SPI_TRANSFER0_START | SPI_CA_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -442,9 +442,9 @@ int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_CADI_MODE0);
+                    SPI_TRANSFER0_START | SPI_CADI_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -497,9 +497,9 @@ int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_CA_MODE0);
+                    SPI_TRANSFER0_START | SPI_CA_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -523,7 +523,7 @@ int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
        dev_dbg(rtsx_dev(chip), "spi_get_status: err_code = 0x%x\n",
                spi->err_code);
        rtsx_stor_set_xfer_buf(&spi->err_code,
-                       min_t(int, scsi_bufflen(srb), 1), srb);
+                              min_t(int, scsi_bufflen(srb), 1), srb);
        scsi_set_resid(srb, scsi_bufflen(srb) - 1);
 
        return STATUS_SUCCESS;
@@ -574,37 +574,37 @@ int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
        rtsx_init_cmd(chip);
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
-               PINGPONG_BUFFER);
+                    PINGPONG_BUFFER);
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
 
        if (len == 0) {
                if (srb->cmnd[9]) {
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
-                                     0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
+                                    0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
                } else {
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
-                                     0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
+                                    0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
                }
        } else {
                if (srb->cmnd[9]) {
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                               SPI_TRANSFER0_START | SPI_CADI_MODE0);
+                                    SPI_TRANSFER0_START | SPI_CADI_MODE0);
                } else {
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                               SPI_TRANSFER0_START | SPI_CDI_MODE0);
+                                    SPI_TRANSFER0_START | SPI_CDI_MODE0);
                }
        }
 
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval < 0) {
@@ -682,38 +682,38 @@ int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 
                if (slow_read) {
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
-                               (u8)addr);
+                                    (u8)addr);
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
-                               (u8)(addr >> 8));
+                                    (u8)(addr >> 8));
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
-                               (u8)(addr >> 16));
+                                    (u8)(addr >> 16));
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-                               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
                } else {
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
-                               (u8)addr);
+                                    (u8)addr);
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
-                               (u8)(addr >> 8));
+                                    (u8)(addr >> 8));
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
-                               (u8)(addr >> 16));
+                                    (u8)(addr >> 16));
                        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-                               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
+                                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
                }
 
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
-                       (u8)(pagelen >> 8));
+                            (u8)(pagelen >> 8));
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
-                       (u8)pagelen);
+                            (u8)pagelen);
 
                rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-                       SPI_TRANSFER0_START | SPI_CADI_MODE0);
+                            SPI_TRANSFER0_START | SPI_CADI_MODE0);
                rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
-                       SPI_TRANSFER0_END, SPI_TRANSFER0_END);
+                            SPI_TRANSFER0_END, SPI_TRANSFER0_END);
 
                rtsx_send_cmd_no_wait(chip);
 
                retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
-                                       DMA_FROM_DEVICE, 10000);
+                                           DMA_FROM_DEVICE, 10000);
                if (retval < 0) {
                        kfree(buf);
                        rtsx_clear_spi_error(chip);
@@ -723,7 +723,7 @@ int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
                }
 
                rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
-                                       TO_XFER_BUF);
+                                         TO_XFER_BUF);
 
                addr += pagelen;
                len -= pagelen;
@@ -775,14 +775,14 @@ int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
                        }
 
                        rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
-                                               FROM_XFER_BUF);
+                                                 FROM_XFER_BUF);
 
                        rtsx_init_cmd(chip);
 
                        rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
-                               0x01, PINGPONG_BUFFER);
+                                    0x01, PINGPONG_BUFFER);
                        rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
-                               buf[0]);
+                                    buf[0]);
                        sf_program(chip, ins, 1, addr, 1);
 
                        retval = rtsx_send_cmd(chip, 0, 100);
@@ -824,14 +824,14 @@ int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 
                while (len) {
                        rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
-                                               FROM_XFER_BUF);
+                                                 FROM_XFER_BUF);
 
                        rtsx_init_cmd(chip);
 
                        rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
-                               0x01, PINGPONG_BUFFER);
+                                    0x01, PINGPONG_BUFFER);
                        rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
-                               buf[0]);
+                                    buf[0]);
                        if (first_byte) {
                                sf_program(chip, ins, 1, addr, 1);
                                first_byte = 0;
@@ -899,10 +899,10 @@ int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
                        rtsx_send_cmd_no_wait(chip);
 
                        rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
-                                               &offset, FROM_XFER_BUF);
+                                                 &offset, FROM_XFER_BUF);
 
                        retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
-                                               DMA_TO_DEVICE, 100);
+                                                   DMA_TO_DEVICE, 100);
                        if (retval < 0) {
                                kfree(buf);
                                rtsx_clear_spi_error(chip);
@@ -1010,18 +1010,18 @@ int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
        rtsx_init_cmd(chip);
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
-               PINGPONG_BUFFER);
+                    PINGPONG_BUFFER);
 
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
-               SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
+                    SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
        rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
        rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
-               SPI_TRANSFER0_START | SPI_CDO_MODE0);
+                    SPI_TRANSFER0_START | SPI_CDO_MODE0);
        rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
-               SPI_TRANSFER0_END);
+                    SPI_TRANSFER0_END);
 
        retval = rtsx_send_cmd(chip, 0, 100);
        if (retval != STATUS_SUCCESS) {
Domain: System / Kernel; Licenses: GPL-2.0;