ARM: dts: lan966x: add flexcom SPI nodes
authorMichael Walle <michael@walle.cc>
Mon, 2 May 2022 22:41:19 +0000 (00:41 +0200)
committerClaudiu Beznea <claudiu.beznea@microchip.com>
Fri, 13 May 2022 13:41:34 +0000 (16:41 +0300)
Add all the SPI nodes for the flexcom IP block. Keep them
disabled by default.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-6-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
arch/arm/boot/dts/lan966x.dtsi

index d7eacb0..a61d394 100644 (file)
                                atmel,fifo-size = <32>;
                                status = "disabled";
                        };
+
+                       spi0: spi@400 {
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0x400 0x200>;
+                               interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
+                                      <&dma0 AT91_XDMAC_DT_PERID(2)>;
+                               dma-names = "tx", "rx";
+                               clocks = <&nic_clk>;
+                               clock-names = "spi_clk";
+                               atmel,fifo-size = <32>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                flx1: flexcom@e0044000 {
                                atmel,fifo-size = <32>;
                                status = "disabled";
                        };
+
+                       spi1: spi@400 {
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0x400 0x200>;
+                               interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
+                                      <&dma0 AT91_XDMAC_DT_PERID(4)>;
+                               dma-names = "tx", "rx";
+                               clocks = <&nic_clk>;
+                               clock-names = "spi_clk";
+                               atmel,fifo-size = <32>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                trng: rng@e0048000 {
                                atmel,fifo-size = <32>;
                                status = "disabled";
                        };
+
+                       spi2: spi@400 {
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0x400 0x200>;
+                               interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
+                                      <&dma0 AT91_XDMAC_DT_PERID(6)>;
+                               dma-names = "tx", "rx";
+                               clocks = <&nic_clk>;
+                               clock-names = "spi_clk";
+                               atmel,fifo-size = <32>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                flx3: flexcom@e0064000 {
                                atmel,fifo-size = <32>;
                                status = "disabled";
                        };
+
+                       spi3: spi@400 {
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0x400 0x200>;
+                               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
+                                      <&dma0 AT91_XDMAC_DT_PERID(8)>;
+                               dma-names = "tx", "rx";
+                               clocks = <&nic_clk>;
+                               clock-names = "spi_clk";
+                               atmel,fifo-size = <32>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                dma0: dma-controller@e0068000 {
                                atmel,fifo-size = <32>;
                                status = "disabled";
                        };
+
+                       spi4: spi@400 {
+                               compatible = "atmel,at91rm9200-spi";
+                               reg = <0x400 0x200>;
+                               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
+                                      <&dma0 AT91_XDMAC_DT_PERID(10)>;
+                               dma-names = "tx", "rx";
+                               clocks = <&nic_clk>;
+                               clock-names = "spi_clk";
+                               atmel,fifo-size = <32>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
                };
 
                timer0: timer@e008c000 {