--- /dev/null
+//===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'A', Atomic
+// Instructions extension.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
+ : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
+ (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, (${rs1})"> {
+ let rs2 = 0;
+}
+
+multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
+ def "" : LR_r<0, 0, funct3, opcodestr>;
+ def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
+ def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
+ def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
+class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
+ : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
+ (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+ opcodestr, "$rd, $rs2, (${rs1})">;
+
+multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
+ def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
+ def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
+ def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
+ def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtA] in {
+defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
+defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
+defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
+defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
+defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
+defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
+defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
+defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
+defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
+defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
+defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
+} // Predicates = [HasStdExtA]
--- /dev/null
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+a < %s \
+# RUN: | llvm-objdump -mattr=+a -d - | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \
+# RUN: | llvm-objdump -mattr=+a -d - | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: lr.w t0, (t1)
+# CHECK: encoding: [0xaf,0x22,0x03,0x10]
+lr.w t0, (t1)
+# CHECK-INST: lr.w.aq t1, (t2)
+# CHECK: encoding: [0x2f,0xa3,0x03,0x14]
+lr.w.aq t1, (t2)
+# CHECK-INST: lr.w.rl t2, (t3)
+# CHECK: encoding: [0xaf,0x23,0x0e,0x12]
+lr.w.rl t2, (t3)
+# CHECK-INST: lr.w.aqrl t3, (t4)
+# CHECK: encoding: [0x2f,0xae,0x0e,0x16]
+lr.w.aqrl t3, (t4)
+
+# CHECK-INST: sc.w t6, t5, (t4)
+# CHECK: encoding: [0xaf,0xaf,0xee,0x19]
+sc.w t6, t5, (t4)
+# CHECK-INST: sc.w.aq t5, t4, (t3)
+# CHECK: encoding: [0x2f,0x2f,0xde,0x1d]
+sc.w.aq t5, t4, (t3)
+# CHECK-INST: sc.w.rl t4, t3, (t2)
+# CHECK: encoding: [0xaf,0xae,0xc3,0x1b]
+sc.w.rl t4, t3, (t2)
+# CHECK-INST: sc.w.aqrl t3, t2, (t1)
+# CHECK: encoding: [0x2f,0x2e,0x73,0x1e]
+sc.w.aqrl t3, t2, (t1)
+
+# CHECK-INST: amoswap.w a4, ra, (s0)
+# CHECK: encoding: [0x2f,0x27,0x14,0x08]
+amoswap.w a4, ra, (s0)
+# CHECK-INST: amoadd.w a1, a2, (a3)
+# CHECK: encoding: [0xaf,0xa5,0xc6,0x00]
+amoadd.w a1, a2, (a3)
+# CHECK-INST: amoxor.w a2, a3, (a4)
+# CHECK: encoding: [0x2f,0x26,0xd7,0x20]
+amoxor.w a2, a3, (a4)
+# CHECK-INST: amoand.w a3, a4, (a5)
+# CHECK: encoding: [0xaf,0xa6,0xe7,0x60]
+amoand.w a3, a4, (a5)
+# CHECK-INST: amoor.w a4, a5, (a6)
+# CHECK: encoding: [0x2f,0x27,0xf8,0x40]
+amoor.w a4, a5, (a6)
+# CHECK-INST: amomin.w a5, a6, (a7)
+# CHECK: encoding: [0xaf,0xa7,0x08,0x81]
+amomin.w a5, a6, (a7)
+# CHECK-INST: amomax.w s7, s6, (s5)
+# CHECK: encoding: [0xaf,0xab,0x6a,0xa1]
+amomax.w s7, s6, (s5)
+# CHECK-INST: amominu.w s6, s5, (s4)
+# CHECK: encoding: [0x2f,0x2b,0x5a,0xc1]
+amominu.w s6, s5, (s4)
+# CHECK-INST: amomaxu.w s5, s4, (s3)
+# CHECK: encoding: [0xaf,0xaa,0x49,0xe1]
+amomaxu.w s5, s4, (s3)
+
+# CHECK-INST: amoswap.w.aq a4, ra, (s0)
+# CHECK: encoding: [0x2f,0x27,0x14,0x0c]
+amoswap.w.aq a4, ra, (s0)
+# CHECK-INST: amoadd.w.aq a1, a2, (a3)
+# CHECK: encoding: [0xaf,0xa5,0xc6,0x04]
+amoadd.w.aq a1, a2, (a3)
+# CHECK-INST: amoxor.w.aq a2, a3, (a4)
+# CHECK: encoding: [0x2f,0x26,0xd7,0x24]
+amoxor.w.aq a2, a3, (a4)
+# CHECK-INST: amoand.w.aq a3, a4, (a5)
+# CHECK: encoding: [0xaf,0xa6,0xe7,0x64]
+amoand.w.aq a3, a4, (a5)
+# CHECK-INST: amoor.w.aq a4, a5, (a6)
+# CHECK: encoding: [0x2f,0x27,0xf8,0x44]
+amoor.w.aq a4, a5, (a6)
+# CHECK-INST: amomin.w.aq a5, a6, (a7)
+# CHECK: encoding: [0xaf,0xa7,0x08,0x85]
+amomin.w.aq a5, a6, (a7)
+# CHECK-INST: amomax.w.aq s7, s6, (s5)
+# CHECK: encoding: [0xaf,0xab,0x6a,0xa5]
+amomax.w.aq s7, s6, (s5)
+# CHECK-INST: amominu.w.aq s6, s5, (s4)
+# CHECK: encoding: [0x2f,0x2b,0x5a,0xc5]
+amominu.w.aq s6, s5, (s4)
+# CHECK-INST: amomaxu.w.aq s5, s4, (s3)
+# CHECK: encoding: [0xaf,0xaa,0x49,0xe5]
+amomaxu.w.aq s5, s4, (s3)
+
+# CHECK-INST: amoswap.w.rl a4, ra, (s0)
+# CHECK: encoding: [0x2f,0x27,0x14,0x0a]
+amoswap.w.rl a4, ra, (s0)
+# CHECK-INST: amoadd.w.rl a1, a2, (a3)
+# CHECK: encoding: [0xaf,0xa5,0xc6,0x02]
+amoadd.w.rl a1, a2, (a3)
+# CHECK-INST: amoxor.w.rl a2, a3, (a4)
+# CHECK: encoding: [0x2f,0x26,0xd7,0x22]
+amoxor.w.rl a2, a3, (a4)
+# CHECK-INST: amoand.w.rl a3, a4, (a5)
+# CHECK: encoding: [0xaf,0xa6,0xe7,0x62]
+amoand.w.rl a3, a4, (a5)
+# CHECK-INST: amoor.w.rl a4, a5, (a6)
+# CHECK: encoding: [0x2f,0x27,0xf8,0x42]
+amoor.w.rl a4, a5, (a6)
+# CHECK-INST: amomin.w.rl a5, a6, (a7)
+# CHECK: encoding: [0xaf,0xa7,0x08,0x83]
+amomin.w.rl a5, a6, (a7)
+# CHECK-INST: amomax.w.rl s7, s6, (s5)
+# CHECK: encoding: [0xaf,0xab,0x6a,0xa3]
+amomax.w.rl s7, s6, (s5)
+# CHECK-INST: amominu.w.rl s6, s5, (s4)
+# CHECK: encoding: [0x2f,0x2b,0x5a,0xc3]
+amominu.w.rl s6, s5, (s4)
+# CHECK-INST: amomaxu.w.rl s5, s4, (s3)
+# CHECK: encoding: [0xaf,0xaa,0x49,0xe3]
+amomaxu.w.rl s5, s4, (s3)
+
+# CHECK-INST: amoswap.w.aqrl a4, ra, (s0)
+# CHECK: encoding: [0x2f,0x27,0x14,0x0e]
+amoswap.w.aqrl a4, ra, (s0)
+# CHECK-INST: amoadd.w.aqrl a1, a2, (a3)
+# CHECK: encoding: [0xaf,0xa5,0xc6,0x06]
+amoadd.w.aqrl a1, a2, (a3)
+# CHECK-INST: amoxor.w.aqrl a2, a3, (a4)
+# CHECK: encoding: [0x2f,0x26,0xd7,0x26]
+amoxor.w.aqrl a2, a3, (a4)
+# CHECK-INST: amoand.w.aqrl a3, a4, (a5)
+# CHECK: encoding: [0xaf,0xa6,0xe7,0x66]
+amoand.w.aqrl a3, a4, (a5)
+# CHECK-INST: amoor.w.aqrl a4, a5, (a6)
+# CHECK: encoding: [0x2f,0x27,0xf8,0x46]
+amoor.w.aqrl a4, a5, (a6)
+# CHECK-INST: amomin.w.aqrl a5, a6, (a7)
+# CHECK: encoding: [0xaf,0xa7,0x08,0x87]
+amomin.w.aqrl a5, a6, (a7)
+# CHECK-INST: amomax.w.aqrl s7, s6, (s5)
+# CHECK: encoding: [0xaf,0xab,0x6a,0xa7]
+amomax.w.aqrl s7, s6, (s5)
+# CHECK-INST: amominu.w.aqrl s6, s5, (s4)
+# CHECK: encoding: [0x2f,0x2b,0x5a,0xc7]
+amominu.w.aqrl s6, s5, (s4)
+# CHECK-INST: amomaxu.w.aqrl s5, s4, (s3)
+# CHECK: encoding: [0xaf,0xaa,0x49,0xe7]
+amomaxu.w.aqrl s5, s4, (s3)