[ARM] Regnereate armv8.2a-fp16-vector-intrinsics.ll test. NFC

diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
index 789a6d6..37e3488 100644 (file)
--- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=arm-eabi -mattr=+v8.2a,+neon,+fullfp16 -float-abi=hard < %s | FileCheck %s
 
 %struct.float16x4x2_t = type { [2 x <4 x half>] }
@@ -5,7 +6,9 @@
 
 define dso_local <4 x half> @test_vabs_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vabs_f16:
-; CHECK:         vabs.f16 d0, d0
+; CHECK-LABEL: test_vabs_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabs.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vabs1.i = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
@@ -14,7 +17,9 @@ entry:
 
 define dso_local <8 x half> @test_vabsq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vabsq_f16:
-; CHECK:         vabs.f16 q0, q0
+; CHECK-LABEL: test_vabsq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabs.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
@@ -23,7 +28,9 @@ entry:
 
 define dso_local <4 x i16> @test_vceqz_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vceqz_f16:
-; CHECK:         vceq.f16 d0, d0, #0
+; CHECK-LABEL: test_vceqz_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vceq.f16 d0, d0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp oeq <4 x half> %a, zeroinitializer
@@ -33,7 +40,9 @@ entry:
 
 define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vceqzq_f16:
-; CHECK:         vceq.f16 q0, q0, #0
+; CHECK-LABEL: test_vceqzq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vceq.f16 q0, q0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp oeq <8 x half> %a, zeroinitializer
@@ -43,7 +52,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcgez_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vcgez_f16:
-; CHECK:         vcge.f16 d0, d0, #0
+; CHECK-LABEL: test_vcgez_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcge.f16 d0, d0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp oge <4 x half> %a, zeroinitializer
@@ -53,7 +64,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vcgezq_f16:
-; CHECK:         vcge.f16 q0, q0, #0
+; CHECK-LABEL: test_vcgezq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcge.f16 q0, q0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp oge <8 x half> %a, zeroinitializer
@@ -63,7 +76,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vcgtz_f16:
-; CHECK:         vcgt.f16 d0, d0, #0
+; CHECK-LABEL: test_vcgtz_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcgt.f16 d0, d0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp ogt <4 x half> %a, zeroinitializer
@@ -73,7 +88,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vcgtzq_f16:
-; CHECK:         vcgt.f16 q0, q0, #0
+; CHECK-LABEL: test_vcgtzq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcgt.f16 q0, q0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp ogt <8 x half> %a, zeroinitializer
@@ -83,7 +100,9 @@ entry:
 
 define dso_local <4 x i16> @test_vclez_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vclez_f16:
-; CHECK:         vcle.f16 d0, d0, #0
+; CHECK-LABEL: test_vclez_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcle.f16 d0, d0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp ole <4 x half> %a, zeroinitializer
@@ -93,7 +112,9 @@ entry:
 
 define dso_local <8 x i16> @test_vclezq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vclezq_f16:
-; CHECK:         vcle.f16 q0, q0, #0
+; CHECK-LABEL: test_vclezq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcle.f16 q0, q0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp ole <8 x half> %a, zeroinitializer
@@ -103,7 +124,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcltz_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vcltz_f16:
-; CHECK:         vclt.f16 d0, d0, #0
+; CHECK-LABEL: test_vcltz_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vclt.f16 d0, d0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp olt <4 x half> %a, zeroinitializer
@@ -113,7 +136,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vcltzq_f16:
-; CHECK:         vclt.f16 q0, q0, #0
+; CHECK-LABEL: test_vcltzq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vclt.f16 q0, q0, #0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = fcmp olt <8 x half> %a, zeroinitializer
@@ -123,7 +148,8 @@ entry:
 
 define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> %a) {
 ; CHECK-LABEL: test_vcvt_f16_s16:
-; CHECK:         vcvt.f16.s16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.s16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = sitofp <4 x i16> %a to <4 x half>
@@ -132,7 +158,8 @@ entry:
 
 define dso_local <8 x half> @test_vcvtq_f16_s16(<8 x i16> %a) {
 ; CHECK-LABEL: test_vcvtq_f16_s16:
-; CHECK:         vcvt.f16.s16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = sitofp <8 x i16> %a to <8 x half>
@@ -141,7 +168,8 @@ entry:
 
 define dso_local <4 x half> @test_vcvt_f16_u16(<4 x i16> %a) {
 ; CHECK-LABEL: test_vcvt_f16_u16:
-; CHECK:         vcvt.f16.u16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.u16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = uitofp <4 x i16> %a to <4 x half>
@@ -150,7 +178,8 @@ entry:
 
 define dso_local <8 x half> @test_vcvtq_f16_u16(<8 x i16> %a) {
 ; CHECK-LABEL: test_vcvtq_f16_u16:
-; CHECK:         vcvt.f16.u16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = uitofp <8 x i16> %a to <8 x half>
@@ -159,7 +188,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvt_s16_f16:
-; CHECK:         vcvt.s16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.s16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = fptosi <4 x half> %a to <4 x i16>
@@ -168,7 +198,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtq_s16_f16:
-; CHECK:         vcvt.s16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.s16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = fptosi <8 x half> %a to <8 x i16>
@@ -177,7 +208,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvt_u16_f16:
-; CHECK:         vcvt.u16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.u16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = fptoui <4 x half> %a to <4 x i16>
@@ -186,7 +218,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtq_u16_f16:
-; CHECK:         vcvt.u16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.u16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt.i = fptoui <8 x half> %a to <8 x i16>
@@ -195,7 +228,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvta_s16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvta_s16_f16:
-; CHECK:         vcvta.s16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvta.s16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvta_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half> %a)
@@ -204,7 +238,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvta_u16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvta_u16_f16:
-; CHECK:         vcvta.u16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvta.u16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvta_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtau.v4i16.v4f16(<4 x half> %a)
@@ -213,7 +248,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtaq_s16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtaq_s16_f16:
-; CHECK:         vcvta.s16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvta.s16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtaq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtas.v8i16.v8f16(<8 x half> %a)
@@ -222,7 +258,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvtm_s16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvtm_s16_f16:
-; CHECK:         vcvtm.s16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtm.s16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtm_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtms.v4i16.v4f16(<4 x half> %a)
@@ -231,7 +268,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtmq_s16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtmq_s16_f16:
-; CHECK:         vcvtm.s16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtm.s16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtmq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtms.v8i16.v8f16(<8 x half> %a)
@@ -240,7 +278,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvtm_u16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvtm_u16_f16:
-; CHECK:         vcvtm.u16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtm.u16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtm_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtmu.v4i16.v4f16(<4 x half> %a)
@@ -249,7 +288,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtmq_u16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtmq_u16_f16:
-; CHECK:         vcvtm.u16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtm.u16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtmq_u16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtmu.v8i16.v8f16(<8 x half> %a)
@@ -258,7 +298,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvtn_s16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvtn_s16_f16:
-; CHECK:         vcvtn.s16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtn.s16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtn_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtns.v4i16.v4f16(<4 x half> %a)
@@ -267,7 +308,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtnq_s16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtnq_s16_f16:
-; CHECK:         vcvtn.s16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtn.s16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtnq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtns.v8i16.v8f16(<8 x half> %a)
@@ -276,7 +318,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvtn_u16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvtn_u16_f16:
-; CHECK:         vcvtn.u16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtn.u16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtn_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtnu.v4i16.v4f16(<4 x half> %a)
@@ -285,7 +328,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtnq_u16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtnq_u16_f16:
-; CHECK:         vcvtn.u16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtn.u16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtnq_u16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtnu.v8i16.v8f16(<8 x half> %a)
@@ -294,7 +338,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvtp_s16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvtp_s16_f16:
-; CHECK:         vcvtp.s16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtp.s16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtp_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtps.v4i16.v4f16(<4 x half> %a)
@@ -303,7 +348,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtpq_s16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtpq_s16_f16:
-; CHECK:         vcvtp.s16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtp.s16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtpq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtps.v8i16.v8f16(<8 x half> %a)
@@ -312,7 +358,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcvtp_u16_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vcvtp_u16_f16:
-; CHECK:         vcvtp.u16.f16 d0, d0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtp.u16.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtp_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtpu.v4i16.v4f16(<4 x half> %a)
@@ -321,7 +368,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcvtpq_u16_f16(<8 x half> %a) {
 ; CHECK-LABEL: test_vcvtpq_u16_f16:
-; CHECK:         vcvtp.u16.f16 q0, q0
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvtp.u16.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvtpq_u16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtpu.v8i16.v8f16(<8 x half> %a)
@@ -330,7 +378,9 @@ entry:
 
 define dso_local <4 x half> @test_vneg_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vneg_f16:
-; CHECK:         vneg.f16 d0, d0
+; CHECK-LABEL: test_vneg_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vneg.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %sub.i = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a
@@ -339,7 +389,9 @@ entry:
 
 define dso_local <8 x half> @test_vnegq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vnegq_f16:
-; CHECK:         vneg.f16 q0, q0
+; CHECK-LABEL: test_vnegq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vneg.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %sub.i = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a
@@ -348,7 +400,9 @@ entry:
 
 define dso_local <4 x half> @test_vrecpe_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrecpe_f16:
-; CHECK:         vrecpe.f16 d0, d0
+; CHECK-LABEL: test_vrecpe_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrecpe.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrecpe_v1.i = tail call <4 x half> @llvm.arm.neon.vrecpe.v4f16(<4 x half> %a)
@@ -357,7 +411,9 @@ entry:
 
 define dso_local <8 x half> @test_vrecpeq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrecpeq_f16:
-; CHECK:         vrecpe.f16 q0, q0
+; CHECK-LABEL: test_vrecpeq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrecpe.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrecpeq_v1.i = tail call <8 x half> @llvm.arm.neon.vrecpe.v8f16(<8 x half> %a)
@@ -366,7 +422,9 @@ entry:
 
 define dso_local <4 x half> @test_vrnd_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrnd_f16:
-; CHECK:         vrintz.f16 d0, d0
+; CHECK-LABEL: test_vrnd_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintz.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrnd_v1.i = tail call <4 x half> @llvm.arm.neon.vrintz.v4f16(<4 x half> %a)
@@ -375,7 +433,9 @@ entry:
 
 define dso_local <8 x half> @test_vrndq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrndq_f16:
-; CHECK:         vrintz.f16 q0, q0
+; CHECK-LABEL: test_vrndq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintz.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintz.v8f16(<8 x half> %a)
@@ -384,7 +444,9 @@ entry:
 
 define dso_local <4 x half> @test_vrnda_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrnda_f16:
-; CHECK:         vrinta.f16 d0, d0
+; CHECK-LABEL: test_vrnda_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrinta.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrnda_v1.i = tail call <4 x half> @llvm.arm.neon.vrinta.v4f16(<4 x half> %a)
@@ -393,7 +455,9 @@ entry:
 
 define dso_local <8 x half> @test_vrndaq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrndaq_f16:
-; CHECK:         vrinta.f16 q0, q0
+; CHECK-LABEL: test_vrndaq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrinta.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndaq_v1.i = tail call <8 x half> @llvm.arm.neon.vrinta.v8f16(<8 x half> %a)
@@ -402,7 +466,9 @@ entry:
 
 define dso_local <4 x half> @test_vrndm_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrndm_f16:
-; CHECK:         vrintm.f16 d0, d0
+; CHECK-LABEL: test_vrndm_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintm.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndm_v1.i = tail call <4 x half> @llvm.arm.neon.vrintm.v4f16(<4 x half> %a)
@@ -411,7 +477,9 @@ entry:
 
 define dso_local <8 x half> @test_vrndmq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrndmq_f16:
-; CHECK:         vrintm.f16 q0, q0
+; CHECK-LABEL: test_vrndmq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintm.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndmq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintm.v8f16(<8 x half> %a)
@@ -420,7 +488,9 @@ entry:
 
 define dso_local <4 x half> @test_vrndn_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrndn_f16:
-; CHECK:         vrintn.f16 d0, d0
+; CHECK-LABEL: test_vrndn_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintn.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndn_v1.i = tail call <4 x half> @llvm.arm.neon.vrintn.v4f16(<4 x half> %a)
@@ -429,7 +499,9 @@ entry:
 
 define dso_local <8 x half> @test_vrndnq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrndnq_f16:
-; CHECK:         vrintn.f16 q0, q0
+; CHECK-LABEL: test_vrndnq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintn.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndnq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintn.v8f16(<8 x half> %a)
@@ -438,7 +510,9 @@ entry:
 
 define dso_local <4 x half> @test_vrndp_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrndp_f16:
-; CHECK:         vrintp.f16 d0, d0
+; CHECK-LABEL: test_vrndp_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintp.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndp_v1.i = tail call <4 x half> @llvm.arm.neon.vrintp.v4f16(<4 x half> %a)
@@ -447,7 +521,9 @@ entry:
 
 define dso_local <8 x half> @test_vrndpq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrndpq_f16:
-; CHECK:         vrintp.f16 q0, q0
+; CHECK-LABEL: test_vrndpq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintp.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndpq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintp.v8f16(<8 x half> %a)
@@ -456,7 +532,9 @@ entry:
 
 define dso_local <4 x half> @test_vrndx_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrndx_f16:
-; CHECK:         vrintx.f16 d0, d0
+; CHECK-LABEL: test_vrndx_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintx.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndx_v1.i = tail call <4 x half> @llvm.arm.neon.vrintx.v4f16(<4 x half> %a)
@@ -465,7 +543,9 @@ entry:
 
 define dso_local <8 x half> @test_vrndxq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrndxq_f16:
-; CHECK:         vrintx.f16 q0, q0
+; CHECK-LABEL: test_vrndxq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrintx.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrndxq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintx.v8f16(<8 x half> %a)
@@ -474,7 +554,9 @@ entry:
 
 define dso_local <4 x half> @test_vrsqrte_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vrsqrte_f16:
-; CHECK:         vrsqrte.f16 d0, d0
+; CHECK-LABEL: test_vrsqrte_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrsqrte.f16 d0, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrsqrte_v1.i = tail call <4 x half> @llvm.arm.neon.vrsqrte.v4f16(<4 x half> %a)
@@ -483,7 +565,9 @@ entry:
 
 define dso_local <8 x half> @test_vrsqrteq_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vrsqrteq_f16:
-; CHECK:         vrsqrte.f16 q0, q0
+; CHECK-LABEL: test_vrsqrteq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrsqrte.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vrsqrteq_v1.i = tail call <8 x half> @llvm.arm.neon.vrsqrte.v8f16(<8 x half> %a)
@@ -492,7 +576,9 @@ entry:
 
 define dso_local <4 x half> @test_vadd_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vadd_f16:
-; CHECK:         vadd.f16 d0, d0, d1
+; CHECK-LABEL: test_vadd_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %add.i = fadd <4 x half> %a, %b
@@ -501,7 +587,9 @@ entry:
 
 define dso_local <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vaddq_f16:
-; CHECK:         vadd.f16 q0, q0, q1
+; CHECK-LABEL: test_vaddq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %add.i = fadd <8 x half> %a, %b
@@ -510,7 +598,9 @@ entry:
 
 define dso_local <4 x half> @test_vabd_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vabd_f16:
-; CHECK:         vabd.f16 d0, d0, d1
+; CHECK-LABEL: test_vabd_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabd.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vabd_v2.i = tail call <4 x half> @llvm.arm.neon.vabds.v4f16(<4 x half> %a, <4 x half> %b)
@@ -519,7 +609,9 @@ entry:
 
 define dso_local <8 x half> @test_vabdq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vabdq_f16:
-; CHECK:         vabd.f16 q0, q0, q1
+; CHECK-LABEL: test_vabdq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabd.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vabdq_v2.i = tail call <8 x half> @llvm.arm.neon.vabds.v8f16(<8 x half> %a, <8 x half> %b)
@@ -528,7 +620,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcage_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vcage_f16:
-; CHECK:         vacge.f16 d0, d0, d1
+; CHECK-LABEL: test_vcage_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vacge.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vcage_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
@@ -537,7 +631,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcageq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcageq_f16:
-; CHECK:         vacge.f16 q0, q0, q1
+; CHECK-LABEL: test_vcageq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vacge.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vcageq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
@@ -546,7 +642,8 @@ entry:
 
 define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vcagt_f16:
-; CHECK:         vacgt.f16 d0, d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vacgt.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
@@ -555,7 +652,8 @@ entry:
 
 define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vcagtq_f16:
-; CHECK:         vacgt.f16 q0, q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vacgt.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
@@ -564,7 +662,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vcale_f16:
-; CHECK:         vacge.f16 d0, d1, d0
+; CHECK-LABEL: test_vcale_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vacge.f16 d0, d1, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcale_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
@@ -573,7 +673,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcaleq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcaleq_f16:
-; CHECK:         vacge.f16 q0, q1, q0
+; CHECK-LABEL: test_vcaleq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vacge.f16 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %vcaleq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
@@ -582,7 +684,9 @@ entry:
 
 define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vceq_f16:
-; CHECK:         vceq.f16 d0, d0, d1
+; CHECK-LABEL: test_vceq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vceq.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp oeq <4 x half> %a, %b
@@ -592,7 +696,9 @@ entry:
 
 define dso_local <8 x i16> @test_vceqq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vceqq_f16:
-; CHECK:         vceq.f16 q0, q0, q1
+; CHECK-LABEL: test_vceqq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vceq.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp oeq <8 x half> %a, %b
@@ -602,7 +708,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcge_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vcge_f16:
-; CHECK:         vcge.f16 d0, d0, d1
+; CHECK-LABEL: test_vcge_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcge.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp oge <4 x half> %a, %b
@@ -612,7 +720,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcgeq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcgeq_f16:
-; CHECK:         vcge.f16 q0, q0, q1
+; CHECK-LABEL: test_vcgeq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcge.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp oge <8 x half> %a, %b
@@ -622,7 +732,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcgt_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vcgt_f16:
-; CHECK:         vcgt.f16 d0, d0, d1
+; CHECK-LABEL: test_vcgt_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcgt.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp ogt <4 x half> %a, %b
@@ -632,7 +744,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcgtq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcgtq_f16:
-; CHECK:         vcgt.f16 q0, q0, q1
+; CHECK-LABEL: test_vcgtq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcgt.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp ogt <8 x half> %a, %b
@@ -642,7 +756,9 @@ entry:
 
 define dso_local <4 x i16> @test_vcle_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vcle_f16:
-; CHECK:         vcge.f16 d0, d1, d0
+; CHECK-LABEL: test_vcle_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcge.f16 d0, d1, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp ole <4 x half> %a, %b
@@ -652,7 +768,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcleq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcleq_f16:
-; CHECK:         vcge.f16 q0, q1, q0
+; CHECK-LABEL: test_vcleq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcge.f16 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp ole <8 x half> %a, %b
@@ -662,7 +780,9 @@ entry:
 
 define dso_local <4 x i16> @test_vclt_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vclt_f16:
-; CHECK:         vcgt.f16 d0, d1, d0
+; CHECK-LABEL: test_vclt_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcgt.f16 d0, d1, d0
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp olt <4 x half> %a, %b
@@ -672,7 +792,9 @@ entry:
 
 define dso_local <8 x i16> @test_vcltq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vcltq_f16:
-; CHECK:         vcgt.f16 q0, q1, q0
+; CHECK-LABEL: test_vcltq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcgt.f16 q0, q1, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %cmp.i = fcmp olt <8 x half> %a, %b
@@ -682,7 +804,9 @@ entry:
 
 define dso_local <4 x half> @test_vcvt_n_f16_s16(<4 x i16> %a) {
 ; CHECKLABEL: test_vcvt_n_f16_s16:
-; CHECK:         vcvt.f16.s16 d0, d0, #2
+; CHECK-LABEL: test_vcvt_n_f16_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.s16 d0, d0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <4 x half> @llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16> %a, i32 2)
@@ -693,7 +817,9 @@ declare <4 x half> @llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16>, i32) #2
 
 define dso_local <8 x half> @test_vcvtq_n_f16_s16(<8 x i16> %a) {
 ; CHECKLABEL: test_vcvtq_n_f16_s16:
-; CHECK:         vcvt.f16.s16 q0, q0, #2
+; CHECK-LABEL: test_vcvtq_n_f16_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.s16 q0, q0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <8 x half> @llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16> %a, i32 2)
@@ -704,7 +830,9 @@ declare <8 x half> @llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16>, i32) #2
 
 define dso_local <4 x half> @test_vcvt_n_f16_u16(<4 x i16> %a) {
 ; CHECKLABEL: test_vcvt_n_f16_u16:
-; CHECK:         vcvt.f16.u16 d0, d0, #2
+; CHECK-LABEL: test_vcvt_n_f16_u16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.u16 d0, d0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <4 x half> @llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16> %a, i32 2)
@@ -715,7 +843,9 @@ declare <4 x half> @llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16>, i32) #2
 
 define dso_local <8 x half> @test_vcvtq_n_f16_u16(<8 x i16> %a) {
 ; CHECKLABEL: test_vcvtq_n_f16_u16:
-; CHECK:         vcvt.f16.u16 q0, q0, #2
+; CHECK-LABEL: test_vcvtq_n_f16_u16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.f16.u16 q0, q0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <8 x half> @llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16> %a, i32 2)
@@ -726,7 +856,9 @@ declare <8 x half> @llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16>, i32) #2
 
 define dso_local <4 x i16> @test_vcvt_n_s16_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vcvt_n_s16_f16:
-; CHECK:         vcvt.s16.f16 d0, d0, #2
+; CHECK-LABEL: test_vcvt_n_s16_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.s16.f16 d0, d0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <4 x i16> @llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half> %a, i32 2)
@@ -737,7 +869,9 @@ declare <4 x i16> @llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half>, i32) #2
 
 define dso_local <8 x i16> @test_vcvtq_n_s16_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vcvtq_n_s16_f16:
-; CHECK:         vcvt.s16.f16 q0, q0, #2
+; CHECK-LABEL: test_vcvtq_n_s16_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <8 x i16> @llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half> %a, i32 2)
@@ -748,7 +882,9 @@ declare <8 x i16> @llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half>, i32) #2
 
 define dso_local <4 x i16> @test_vcvt_n_u16_f16(<4 x half> %a) {
 ; CHECKLABEL: test_vcvt_n_u16_f16:
-; CHECK:         vcvt.u16.f16 d0, d0, #2
+; CHECK-LABEL: test_vcvt_n_u16_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.u16.f16 d0, d0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <4 x i16> @llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half> %a, i32 2)
@@ -759,7 +895,9 @@ declare <4 x i16> @llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half>, i32) #2
 
 define dso_local <8 x i16> @test_vcvtq_n_u16_f16(<8 x half> %a) {
 ; CHECKLABEL: test_vcvtq_n_u16_f16:
-; CHECK:         vcvt.u16.f16 q0, q0, #2
+; CHECK-LABEL: test_vcvtq_n_u16_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vcvt_n1 = tail call <8 x i16> @llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half> %a, i32 2)
@@ -770,7 +908,9 @@ declare <8 x i16> @llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half>, i32) #2
 
 define dso_local <4 x half> @test_vmax_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vmax_f16:
-; CHECK:         vmax.f16 d0, d0, d1
+; CHECK-LABEL: test_vmax_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vmax_v2.i = tail call <4 x half> @llvm.arm.neon.vmaxs.v4f16(<4 x half> %a, <4 x half> %b)
@@ -779,7 +919,9 @@ entry:
 
 define dso_local <8 x half> @test_vmaxq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vmaxq_f16:
-; CHECK:         vmax.f16 q0, q0, q1
+; CHECK-LABEL: test_vmaxq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmax.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vmaxq_v2.i = tail call <8 x half> @llvm.arm.neon.vmaxs.v8f16(<8 x half> %a, <8 x half> %b)
@@ -788,7 +930,8 @@ entry:
 
 define dso_local <4 x half> @test_vmaxnm_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vmaxnm_f16:
-; CHECK:         vmaxnm.f16 d0, d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmaxnm.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vmaxnm_v2.i = tail call <4 x half> @llvm.arm.neon.vmaxnm.v4f16(<4 x half> %a, <4 x half> %b)
@@ -797,7 +940,8 @@ entry:
 
 define dso_local <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vmaxnmq_f16:
-; CHECK:         vmaxnm.f16 q0, q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmaxnm.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vmaxnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vmaxnm.v8f16(<8 x half> %a, <8 x half> %b)
@@ -806,7 +950,8 @@ entry:
 
 define dso_local <4 x half> @test_vmin_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vmin_f16:
-; CHECK:         vmin.f16 d0, d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vmin_v2.i = tail call <4 x half> @llvm.arm.neon.vmins.v4f16(<4 x half> %a, <4 x half> %b)
@@ -815,7 +960,8 @@ entry:
 
 define dso_local <8 x half> @test_vminq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vminq_f16:
-; CHECK:         vmin.f16 q0, q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmin.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vminq_v2.i = tail call <8 x half> @llvm.arm.neon.vmins.v8f16(<8 x half> %a, <8 x half> %b)
@@ -824,7 +970,8 @@ entry:
 
 define dso_local <4 x half> @test_vminnm_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vminnm_f16:
-; CHECK:         vminnm.f16 d0, d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vminnm.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vminnm_v2.i = tail call <4 x half> @llvm.arm.neon.vminnm.v4f16(<4 x half> %a, <4 x half> %b)
@@ -833,7 +980,8 @@ entry:
 
 define dso_local <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vminnmq_f16:
-; CHECK:         vminnm.f16 q0, q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vminnm.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vminnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vminnm.v8f16(<8 x half> %a, <8 x half> %b)
@@ -842,7 +990,9 @@ entry:
 
 define dso_local <4 x half> @test_vmul_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vmul_f16:
-; CHECK:         vmul.f16 d0, d0, d1
+; CHECK-LABEL: test_vmul_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmul.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %mul.i = fmul <4 x half> %a, %b
@@ -851,7 +1001,9 @@ entry:
 
 define dso_local <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vmulq_f16:
-; CHECK:         vmul.f16 q0, q0, q1
+; CHECK-LABEL: test_vmulq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmul.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %mul.i = fmul <8 x half> %a, %b
@@ -860,7 +1012,9 @@ entry:
 
 define dso_local <4 x half> @test_vpadd_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vpadd_f16:
-; CHECK:         vpadd.f16 d0, d0, d1
+; CHECK-LABEL: test_vpadd_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vpadd.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vpadd_v2.i = tail call <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half> %a, <4 x half> %b)
@@ -869,7 +1023,9 @@ entry:
 
 define dso_local <4 x half> @test_vpmax_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vpmax_f16:
-; CHECK:         vpmax.f16 d0, d0, d1
+; CHECK-LABEL: test_vpmax_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vpmax.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vpmax_v2.i = tail call <4 x half> @llvm.arm.neon.vpmaxs.v4f16(<4 x half> %a, <4 x half> %b)
@@ -878,7 +1034,9 @@ entry:
 
 define dso_local <4 x half> @test_vpmin_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vpmin_f16:
-; CHECK:         vpmin.f16 d0, d0, d1
+; CHECK-LABEL: test_vpmin_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vpmin.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vpmin_v2.i = tail call <4 x half> @llvm.arm.neon.vpmins.v4f16(<4 x half> %a, <4 x half> %b)
@@ -887,7 +1045,9 @@ entry:
 
 define dso_local <4 x half> @test_vrecps_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vrecps_f16:
-; CHECK:         vrecps.f16 d0, d0, d1
+; CHECK-LABEL: test_vrecps_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrecps.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vrecps_v2.i = tail call <4 x half> @llvm.arm.neon.vrecps.v4f16(<4 x half> %a, <4 x half> %b)
@@ -896,7 +1056,9 @@ entry:
 
 define dso_local <8 x half> @test_vrecpsq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vrecpsq_f16:
-; CHECK:         vrecps.f16 q0, q0, q1
+; CHECK-LABEL: test_vrecpsq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrecps.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vrecpsq_v2.i = tail call <8 x half> @llvm.arm.neon.vrecps.v8f16(<8 x half> %a, <8 x half> %b)
@@ -905,7 +1067,9 @@ entry:
 
 define dso_local <4 x half> @test_vrsqrts_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vrsqrts_f16:
-; CHECK:         vrsqrts.f16 d0, d0, d1
+; CHECK-LABEL: test_vrsqrts_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrsqrts.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vrsqrts_v2.i = tail call <4 x half> @llvm.arm.neon.vrsqrts.v4f16(<4 x half> %a, <4 x half> %b)
@@ -914,7 +1078,9 @@ entry:
 
 define dso_local <8 x half> @test_vrsqrtsq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vrsqrtsq_f16:
-; CHECK:         vrsqrts.f16 q0, q0, q1
+; CHECK-LABEL: test_vrsqrtsq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrsqrts.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vrsqrtsq_v2.i = tail call <8 x half> @llvm.arm.neon.vrsqrts.v8f16(<8 x half> %a, <8 x half> %b)
@@ -923,7 +1089,9 @@ entry:
 
 define dso_local <4 x half> @test_vsub_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vsub_f16:
-; CHECK:         vsub.f16 d0, d0, d1
+; CHECK-LABEL: test_vsub_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.f16 d0, d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %sub.i = fsub <4 x half> %a, %b
@@ -932,7 +1100,9 @@ entry:
 
 define dso_local <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECKLABEL: test_vsubq_f16:
-; CHECK:         vsub.f16 q0, q0, q1
+; CHECK-LABEL: test_vsubq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vsub.f16 q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %sub.i = fsub <8 x half> %a, %b
@@ -941,7 +1111,8 @@ entry:
 
 define dso_local <4 x half> @test_vfma_f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
 ; CHECK-LABEL: test_vfma_f16:
-; CHECK:         vfma.f16 d0, d1, d2
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vfma.f16 d0, d1, d2
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)
@@ -950,7 +1121,8 @@ entry:
 
 define dso_local <8 x half> @test_vfmaq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
 ; CHECK-LABEL: test_vfmaq_f16:
-; CHECK:         vfma.f16 q0, q1, q2
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vfma.f16 q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)
@@ -959,8 +1131,9 @@ entry:
 
 define dso_local <4 x half> @test_vfms_f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
 ; CHECK-LABEL: test_vfms_f16:
-; CHECK:         vneg.f16 [[D16:d[0-9]+]], d1
-; CHECK-NEXT:    vfma.f16 d0, [[D16]], d2
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vneg.f16 d16, d1
+; CHECK-NEXT:    vfma.f16 d0, d16, d2
 ; CHECK-NEXT:    bx lr
 entry:
   %sub.i = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
@@ -970,8 +1143,9 @@ entry:
 
 define dso_local <8 x half> @test_vfmsq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
 ; CHECK-LABEL: test_vfmsq_f16:
-; CHECK:         vneg.f16 [[Q8:q[0-9]+]], q1
-; CHECK-NEXT:    vfma.f16 q0, [[Q8]], q2
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vneg.f16 q8, q1
+; CHECK-NEXT:    vfma.f16 q0, q8, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %sub.i = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
@@ -981,7 +1155,8 @@ entry:
 
 define dso_local <4 x half> @test_vmul_lane_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vmul_lane_f16:
-; CHECK:         vmul.f16 d0, d0, d1[3]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmul.f16 d0, d0, d1[3]
 ; CHECK-NEXT:    bx lr
 entry:
   %shuffle = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
@@ -991,7 +1166,9 @@ entry:
 
 define dso_local <8 x half> @test_vmulq_lane_f16(<8 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vmulq_lane_f16:
-; CHECK:         vmul.f16 q0, q0, d2[3]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT:    vmul.f16 q0, q0, d2[3]
 ; CHECK-NEXT:    bx lr
 entry:
   %shuffle = shufflevector <4 x half> %b, <4 x half> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
@@ -1001,7 +1178,9 @@ entry:
 
 define dso_local <4 x half> @test_vmul_n_f16(<4 x half> %a, float %b.coerce) {
 ; CHECK-LABEL: test_vmul_n_f16:
-; CHECK:         vmul.f16 d0, d0, d1[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $s2 killed $s2 def $d1
+; CHECK-NEXT:    vmul.f16 d0, d0, d1[0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast float %b.coerce to i32
@@ -1015,7 +1194,9 @@ entry:
 
 define dso_local <8 x half> @test_vmulq_n_f16(<8 x half> %a, float %b.coerce) {
 ; CHECK-LABEL: test_vmulq_n_f16:
-; CHECK:         vmul.f16 q0, q0, d2[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $s4 killed $s4 def $d2
+; CHECK-NEXT:    vmul.f16 q0, q0, d2[0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast float %b.coerce to i32
@@ -1029,7 +1210,9 @@ entry:
 
 define dso_local <4 x half> @test_vbsl_f16(<4 x i16> %a, <4 x half> %b, <4 x half> %c) {
 ; CHECKLABEL: test_vbsl_f16:
-; CHECK:         vbsl d0, d1, d2
+; CHECK-LABEL: test_vbsl_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vbsl d0, d1, d2
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast <4 x i16> %a to <8 x i8>
@@ -1042,7 +1225,9 @@ entry:
 
 define dso_local <8 x half> @test_vbslq_f16(<8 x i16> %a, <8 x half> %b, <8 x half> %c) {
 ; CHECKLABEL: test_vbslq_f16:
-; CHECK:         vbsl q0, q1, q2
+; CHECK-LABEL: test_vbslq_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vbsl q0, q1, q2
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast <8 x i16> %a to <16 x i8>
@@ -1055,7 +1240,8 @@ entry:
 
 define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vzip_f16:
-; CHECK:         vzip.16 d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vzip.16 d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vzip.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
@@ -1067,7 +1253,8 @@ entry:
 
 define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vzipq_f16:
-; CHECK:         vzip.16 q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vzip.16 q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vzip.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
@@ -1079,7 +1266,8 @@ entry:
 
 define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vuzp_f16:
-; CHECK:         vuzp.16 d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vuzp.16 d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vuzp.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -1091,7 +1279,8 @@ entry:
 
 define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vuzpq_f16:
-; CHECK:         vuzp.16 q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vuzp.16 q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vuzp.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -1103,7 +1292,8 @@ entry:
 
 define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vtrn_f16:
-; CHECK:         vtrn.16 d0, d1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vtrn.16 d0, d1
 ; CHECK-NEXT:    bx lr
 entry:
   %vtrn.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
@@ -1115,7 +1305,8 @@ entry:
 
 define dso_local %struct.float16x8x2_t @test_vtrnq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vtrnq_f16:
-; CHECK:         vtrn.16 q0, q1
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vtrn.16 q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %vtrn.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
@@ -1127,7 +1318,9 @@ entry:
 
 define dso_local <4 x half> @test_vmov_n_f16(float %a.coerce) {
 ; CHECK-LABEL: test_vmov_n_f16:
-; CHECK:         vdup.16 d0, d0[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT:    vdup.16 d0, d0[0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast float %a.coerce to i32
@@ -1140,7 +1333,9 @@ entry:
 
 define dso_local <8 x half> @test_vmovq_n_f16(float %a.coerce) {
 ; CHECK-LABEL: test_vmovq_n_f16:
-; CHECK:         vdup.16 q0, d0[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT:    vdup.16 q0, d0[0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast float %a.coerce to i32
@@ -1153,7 +1348,9 @@ entry:
 
 define dso_local <4 x half> @test_vdup_n_f16(float %a.coerce) {
 ; CHECK-LABEL: test_vdup_n_f16:
-; CHECK:         vdup.16 d0, d0[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT:    vdup.16 d0, d0[0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast float %a.coerce to i32
@@ -1166,7 +1363,9 @@ entry:
 
 define dso_local <8 x half> @test_vdupq_n_f16(float %a.coerce) {
 ; CHECK-LABEL: test_vdupq_n_f16:
-; CHECK:        vdup.16 q0, d0[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT:    vdup.16 q0, d0[0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = bitcast float %a.coerce to i32
@@ -1179,7 +1378,8 @@ entry:
 
 define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vdup_lane_f16:
-; CHECK:         vdup.32 d0, d0[3]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vdup.32 d0, d0[3]
 ; CHECK-NEXT:    bx lr
 entry:
   %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
@@ -1188,7 +1388,9 @@ entry:
 
 define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vdupq_lane_f16:
-; CHECK:         vdup.16 q0, d0[3]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    vdup.16 q0, d0[3]
 ; CHECK-NEXT:    bx lr
 entry:
   %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
@@ -1197,7 +1399,8 @@ entry:
 
 define dso_local <4 x half> @test_vext_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: test_vext_f16:
-; CHECK:         vext.16 d0, d0, d1, #2
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vext.16 d0, d0, d1, #2
 ; CHECK-NEXT:    bx lr
 entry:
   %vext = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
@@ -1206,7 +1409,8 @@ entry:
 
 define dso_local <8 x half> @test_vextq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test_vextq_f16:
-; CHECK:         vext.16 q0, q0, q1, #5
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vext.16 q0, q0, q1, #5
 ; CHECK-NEXT:    bx lr
 entry:
   %vext = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
@@ -1214,12 +1418,20 @@ entry:
 }
 
 define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
+; CHECK-LABEL: test_vrev64_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev64.16 d0, d0
+; CHECK-NEXT:    bx lr
 entry:
   %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x half> %shuffle.i
 }
 
 define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
+; CHECK-LABEL: test_vrev64q_f16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vrev64.16 q0, q0
+; CHECK-NEXT:    bx lr
 entry:
   %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
   ret <8 x half> %shuffle.i
@@ -1227,8 +1439,9 @@ entry:
 
 define <4 x half> @test_vld_dup1_4xhalf(half* %b) {
 ; CHECK-LABEL: test_vld_dup1_4xhalf:
-; CHECK:       vld1.16 {d0[]}, [r0:16]
-; CHECK-NEXT:  bx      lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vld1.16 {d0[]}, [r0:16]
+; CHECK-NEXT:    bx lr
 
 entry:
   %b1 = load half, half* %b, align 2
@@ -1241,8 +1454,9 @@ entry:
 
 define <8 x half> @test_vld_dup1_8xhalf(half* %b) local_unnamed_addr {
 ; CHECK-LABEL: test_vld_dup1_8xhalf:
-; CHECK:       vld1.16 {d0[], d1[]}, [r0:16]
-; CHECK-NEXT:  bx      lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vld1.16 {d0[], d1[]}, [r0:16]
+; CHECK-NEXT:    bx lr
 
 entry:
   %b1 = load half, half* %b, align 2
@@ -1253,8 +1467,10 @@ entry:
 
 define <8 x half> @test_shufflevector8xhalf(<4 x half> %a) {
 ; CHECK-LABEL: test_shufflevector8xhalf:
-; CHECK:       vmov.f64        d1, d0
-; CHECK-NEXT:  bx      lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    vmov.f64 d1, d0
+; CHECK-NEXT:    bx lr
 
 entry:
   %r = shufflevector <4 x half> %a, <4 x half> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -1334,7 +1550,10 @@ declare void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, <4
 
 define { <8 x half>, <8 x half> } @test_vld2q_lane_f16(i8*, <8 x half>, <8 x half>) {
 ; CHECK-LABEL: test_vld2q_lane_f16:
-; CHECK:    vld2.16 {d1[3], d3[3]}, [r0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    vld2.16 {d1[3], d3[3]}, [r0]
 ; CHECK-NEXT:    bx lr
 entry:
   %3 = tail call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, i32 7, i32 2)
@@ -1343,8 +1562,11 @@ entry:
 
 define { <4 x half>, <4 x half> } @test_vld2_lane_f16(i8*, <4 x half>, <4 x half>) {
 ; CHECK-LABEL: test_vld2_lane_f16:
-; CHECK:       vld2.16 {d0[3], d1[3]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT:    vld2.16 {d0[3], d1[3]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   %3 = tail call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, i32 3, i32 2)
   ret { <4 x half>, <4 x half> } %3
@@ -1352,8 +1574,12 @@ entry:
 
 define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
 ; CHECK-LABEL: test_vld3q_lane_f16:
-; CHECK:       vld3.16 {d1[3], d3[3], d5[3]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    vld3.16 {d1[3], d3[3], d5[3]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   %4 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 7, i32 2)
   ret { <8 x half>, <8 x half>, <8 x half> } %4
@@ -1361,72 +1587,110 @@ entry:
 
 define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
 ; CHECK-LABEL: test_vld3_lane_f16:
-; CHECK:       vld3.16 {d0[3], d1[3], d2[3]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    vld3.16 {d0[3], d1[3], d2[3]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   %4 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 3, i32 2)
   ret { <4 x half>, <4 x half>, <4 x half> } %4
 }
 define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
 ; CHECK-LABEL: test_vld4lane_v8f16_p0i8:
-; CHECK:       vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   %5 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 7, i32 2)
   ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %5
 }
 define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
 ; CHECK-LABEL: test_vld4lane_v4f16_p0i8:
-; CHECK:       vld4.16 {d0[3], d1[3], d2[3], d3[3]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    vld4.16 {d0[3], d1[3], d2[3], d3[3]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
  %5 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 3, i32 2)
  ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %5
 }
 define void @test_vst2lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>) {
 ; CHECK-LABEL: test_vst2lane_p0i8_v8f16:
-; CHECK:       vst2.16 {d0[0], d2[0]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    vst2.16 {d0[0], d2[0]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   tail call void @llvm.arm.neon.vst2lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, i32 0, i32 1)
   ret void
 }
 define void @test_vst2lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>) {
 ; CHECK-LABEL: test_vst2lane_p0i8_v4f16:
-; CHECK:       vst2.16 {d0[0], d1[0]}, [r0:32]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT:    vst2.16 {d0[0], d1[0]}, [r0:32]
+; CHECK-NEXT:    bx lr
 entry:
   tail call void @llvm.arm.neon.vst2lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, i32 0, i32 0)
   ret void
 }
 define void @test_vst3lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
 ; CHECK-LABEL: test_vst3lane_p0i8_v8f16:
-; CHECK:       vst3.16 {d0[0], d2[0], d4[0]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    vst3.16 {d0[0], d2[0], d4[0]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   tail call void @llvm.arm.neon.vst3lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 0, i32 0)
   ret void
 }
 define void @test_vst3lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
 ; CHECK-LABEL: test_vst3lane_p0i8_v4f16:
-; CHECK:       vst3.16 {d0[0], d1[0], d2[0]}, [r0]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    vst3.16 {d0[0], d1[0], d2[0]}, [r0]
+; CHECK-NEXT:    bx lr
 entry:
   tail call void @llvm.arm.neon.vst3lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 0, i32 0)
   ret void
 }
 define void @test_vst4lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
 ; CHECK-LABEL: test_vst4lane_p0i8_v8f16:
-; CHECK:       vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0:64]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT:    vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0:64]
+; CHECK-NEXT:    bx lr
 entry:
   tail call void @llvm.arm.neon.vst4lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 0, i32 0)
   ret void
 }
 define void @test_vst4lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
 ; CHECK-LABEL: test_vst4lane_p0i8_v4f16:
-; CHECK:       vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r0:64]
-; CHECK-NEXT:  bx lr
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT:    vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r0:64]
+; CHECK-NEXT:    bx lr
 entry:
   tail call void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 0, i32 0)
   ret void