drm/amdgpu: only allow secure submission on rings which support that
authorLang Yu <Lang.Yu@amd.com>
Tue, 15 Mar 2022 05:17:55 +0000 (13:17 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 15 Mar 2022 18:42:27 +0000 (14:42 -0400)
Only GFX ring, SDMA ring and VCN decode ring support secure submission
at the moment.

Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
13 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

index bc1297d..d583766 100644 (file)
@@ -166,8 +166,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        }
 
        if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
-           (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)) {
-               dev_err(adev->dev, "secure submissions not supported on compute rings\n");
+           (!ring->funcs->secure_submission_supported)) {
+               dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
                return -EINVAL;
        }
 
index a8bed1b..5320bb0 100644 (file)
@@ -155,6 +155,7 @@ struct amdgpu_ring_funcs {
        u32                     nop;
        bool                    support_64bit_ptrs;
        bool                    no_user_fence;
+       bool                    secure_submission_supported;
        unsigned                vmhub;
        unsigned                extra_dw;
 
index 713d39d..f4c6acc 100644 (file)
@@ -9377,6 +9377,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
        .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
index 8def7f6..46d4bf2 100644 (file)
@@ -6865,6 +6865,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
        .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
index 4509bd4..1d8bbcb 100644 (file)
@@ -1142,6 +1142,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = false,
+       .secure_submission_supported = true,
        .get_rptr = sdma_v2_4_ring_get_rptr,
        .get_wptr = sdma_v2_4_ring_get_wptr,
        .set_wptr = sdma_v2_4_ring_set_wptr,
index 135727b..4ef4fef 100644 (file)
@@ -1580,6 +1580,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = false,
+       .secure_submission_supported = true,
        .get_rptr = sdma_v3_0_ring_get_rptr,
        .get_wptr = sdma_v3_0_ring_get_wptr,
        .set_wptr = sdma_v3_0_ring_set_wptr,
index 01b3855..d7e8f72 100644 (file)
@@ -2414,6 +2414,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = sdma_v4_0_ring_get_rptr,
        .get_wptr = sdma_v4_0_ring_get_wptr,
@@ -2450,6 +2451,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_1,
        .get_rptr = sdma_v4_0_ring_get_rptr,
        .get_wptr = sdma_v4_0_ring_get_wptr,
@@ -2482,6 +2484,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = sdma_v4_0_ring_get_rptr,
        .get_wptr = sdma_v4_0_page_ring_get_wptr,
@@ -2514,6 +2517,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_1,
        .get_rptr = sdma_v4_0_ring_get_rptr,
        .get_wptr = sdma_v4_0_page_ring_get_wptr,
index 53a8df4..a8d49c0 100644 (file)
@@ -1690,6 +1690,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = sdma_v5_0_ring_get_rptr,
        .get_wptr = sdma_v5_0_ring_get_wptr,
index dcc622e..824eace 100644 (file)
@@ -1687,6 +1687,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
        .align_mask = 0xf,
        .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
        .support_64bit_ptrs = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = sdma_v5_2_ring_get_rptr,
        .get_wptr = sdma_v5_2_ring_get_wptr,
index 7bbb9ba..6c9d5cd 100644 (file)
@@ -1910,6 +1910,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
        .align_mask = 0xf,
        .support_64bit_ptrs = false,
        .no_user_fence = true,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = vcn_v1_0_dec_ring_get_rptr,
        .get_wptr = vcn_v1_0_dec_ring_get_wptr,
index 319ac8e..8cb2124 100644 (file)
@@ -2007,6 +2007,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_DEC,
        .align_mask = 0xf,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = vcn_v2_0_dec_ring_get_rptr,
        .get_wptr = vcn_v2_0_dec_ring_get_wptr,
index 1869bae..1bf6729 100644 (file)
@@ -1515,6 +1515,7 @@ static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_DEC,
        .align_mask = 0xf,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_1,
        .get_rptr = vcn_v2_5_dec_ring_get_rptr,
        .get_wptr = vcn_v2_5_dec_ring_get_wptr,
@@ -1545,6 +1546,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_DEC,
        .align_mask = 0xf,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = vcn_v2_5_dec_ring_get_rptr,
        .get_wptr = vcn_v2_5_dec_ring_get_wptr,
index 5dbf5ba..c87263e 100644 (file)
@@ -1786,6 +1786,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_DEC,
        .align_mask = 0x3f,
        .nop = VCN_DEC_SW_CMD_NO_OP,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = vcn_v3_0_dec_ring_get_rptr,
        .get_wptr = vcn_v3_0_dec_ring_get_wptr,
@@ -1944,6 +1945,7 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_DEC,
        .align_mask = 0xf,
+       .secure_submission_supported = true,
        .vmhub = AMDGPU_MMHUB_0,
        .get_rptr = vcn_v3_0_dec_ring_get_rptr,
        .get_wptr = vcn_v3_0_dec_ring_get_wptr,