};
}
-template<typename MemInst>
-static bool AreSequentialAccesses(MemInst *MemOp0, MemInst *MemOp1,
- const DataLayout &DL, ScalarEvolution &SE) {
- if (isConsecutiveAccess(MemOp0, MemOp1, DL, SE))
- return true;
- return false;
-}
-
bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,
MemInstList &VecMem) {
if (!Ld0 || !Ld1)
if (Base == Offset || OffsetLoads.count(Offset))
continue;
- if (AreSequentialAccesses<LoadInst>(Base, Offset, *DL, *SE) &&
+ if (isConsecutiveAccess(Base, Offset, *DL, *SE) &&
SafeToPair(Base, Offset)) {
LoadPairs[Base] = Offset;
OffsetLoads.insert(Offset);