x86: Add some more common MSR indexes

Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 9654600..950132a 100644 (file)
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -17,6 +17,7 @@
 #include <asm/cpu_x86.h>
 #include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/speedstep.h>
@@ -363,7 +364,7 @@ static void set_max_ratio(void)
                msr = msr_read(MSR_PLATFORM_INFO);
                perf_ctl.lo = msr.lo & 0xff00;
        }
-       msr_write(IA32_PERF_CTL, perf_ctl);
+       msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 
        debug("model_x06ax: frequency set to %d\n",
              ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
@@ -455,7 +456,7 @@ static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
 {
        msr_t msr;
 
-       msr = msr_read(IA32_PERF_CTL);
+       msr = msr_read(MSR_IA32_PERF_CTL);
        info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
        info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
 

diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
index d2f9006..22f7929 100644 (file)
--- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -15,13 +15,9 @@
 #define  CPUID_VMX                     (1 << 5)
 #define  CPUID_SMX                     (1 << 6)
 #define MSR_FEATURE_CONFIG             0x13c
-#define MSR_FLEX_RATIO                 0x194
-#define  FLEX_RATIO_LOCK               (1 << 20)
-#define  FLEX_RATIO_EN                 (1 << 16)
 #define IA32_PLATFORM_DCA_CAP          0x1f8
 #define IA32_MISC_ENABLE               0x1a0
 #define MSR_TEMPERATURE_TARGET         0x1a2
-#define IA32_PERF_CTL                  0x199
 #define IA32_THERM_INTERRUPT           0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS   0x1b0
 #define  ENERGY_POLICY_PERFORMANCE     0
@@ -31,12 +27,8 @@
 #define MSR_LT_LOCK_MEMORY             0x2e7
 #define IA32_MC0_STATUS                0x401
 
-#define MSR_PIC_MSG_CONTROL            0x2e
-#define  PLATFORM_INFO_SET_TDP         (1 << 29)
-
 #define MSR_MISC_PWR_MGMT              0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS     (1 << 0)
-#define MSR_TURBO_RATIO_LIMIT          0x1ad
 
 #define MSR_PKGC3_IRTL                 0x60a
 #define MSR_PKGC6_IRTL                 0x60b
@@ -50,13 +42,6 @@
 #define  IRTL_33554432_NS              (5 << 10)
 #define  IRTL_RESPONSE_MASK            (0x3ff)
 
-/* long duration in low dword, short duration in high dword */
-#define  PKG_POWER_LIMIT_MASK          0x7fff
-#define  PKG_POWER_LIMIT_EN            (1 << 15)
-#define  PKG_POWER_LIMIT_CLAMP         (1 << 16)
-#define  PKG_POWER_LIMIT_TIME_SHIFT    17
-#define  PKG_POWER_LIMIT_TIME_MASK     0x7f
-
 #define MSR_PP0_CURRENT_CONFIG         0x601
 #define  PP0_CURRENT_LIMIT             (112 << 3) /* 112 A */
 #define MSR_PP1_CURRENT_CONFIG         0x602
@@ -65,11 +50,9 @@
 #define MSR_PKG_POWER_SKU              0x614
 
 #define IVB_CONFIG_TDP_MIN_CPUID       0x306a2
-#define MSR_CONFIG_TDP_NOMINAL         0x648
 #define MSR_CONFIG_TDP_LEVEL1          0x649
 #define MSR_CONFIG_TDP_LEVEL2          0x64a
 #define MSR_CONFIG_TDP_CONTROL         0x64b
-#define MSR_TURBO_ACTIVATION_RATIO     0x64c
 
 /* P-state configuration */
 #define PSS_MAX_ENTRIES                        8

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 38dbb31..b2a03f4 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -41,6 +41,9 @@
 #define EFER_FFXSR             (1<<_EFER_FFXSR)
 
 /* Intel MSRs. Some also available on other CPUs */
+#define MSR_PIC_MSG_CONTROL            0x2e
+#define  PLATFORM_INFO_SET_TDP         (1 << 29)
+
 #define MSR_IA32_PERFCTR0              0x000000c1
 #define MSR_IA32_PERFCTR1              0x000000c2
 #define MSR_FSB_FREQ                   0x000000cd
@@ -73,14 +76,27 @@
 #define MSR_IA32_MCG_STATUS            0x0000017a
 #define MSR_IA32_MCG_CTL               0x0000017b
 
+#define MSR_FLEX_RATIO                 0x194
+#define  FLEX_RATIO_LOCK               (1 << 20)
+#define  FLEX_RATIO_EN                 (1 << 16)
+
 #define MSR_IA32_MISC_ENABLES          0x000001a0
+#define MSR_TEMPERATURE_TARGET         0x1a2
 #define MSR_OFFCORE_RSP_0              0x000001a6
 #define MSR_OFFCORE_RSP_1              0x000001a7
+#define MSR_MISC_PWR_MGMT              0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS     (1 << 0)
 #define MSR_NHM_TURBO_RATIO_LIMIT      0x000001ad
 #define MSR_IVT_TURBO_RATIO_LIMIT      0x000001ae
 
+#define MSR_IA32_ENERGY_PERFORMANCE_BIAS       0x1b0
+#define  ENERGY_POLICY_PERFORMANCE     0
+#define  ENERGY_POLICY_NORMAL          6
+#define  ENERGY_POLICY_POWERSAVE       15
+
 #define MSR_LBR_SELECT                 0x000001c8
 #define MSR_LBR_TOS                    0x000001c9
+#define MSR_IA32_PLATFORM_DCA_CAP      0x1f8
 #define MSR_POWER_CTL                  0x000001fc
 #define MSR_LBR_NHM_FROM               0x00000680
 #define MSR_LBR_NHM_TO                 0x000006c0
@@ -147,7 +163,29 @@
 
 #define MSR_PKG_POWER_SKU_UNIT         0x00000606
 
+#define MSR_C_STATE_LATENCY_CONTROL_0  0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1  0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2  0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3  0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4  0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5  0x635
+#define  IRTL_VALID                    (1 << 15)
+#define  IRTL_1_NS                     (0 << 10)
+#define  IRTL_32_NS                    (1 << 10)
+#define  IRTL_1024_NS                  (2 << 10)
+#define  IRTL_32768_NS                 (3 << 10)
+#define  IRTL_1048576_NS               (4 << 10)
+#define  IRTL_33554432_NS              (5 << 10)
+#define  IRTL_RESPONSE_MASK            (0x3ff)
+
 #define MSR_PKG_POWER_LIMIT            0x00000610
+/* long duration in low dword, short duration in high dword */
+#define  PKG_POWER_LIMIT_MASK          0x7fff
+#define  PKG_POWER_LIMIT_EN            (1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP         (1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT    17
+#define  PKG_POWER_LIMIT_TIME_MASK     0x7f
+
 #define MSR_PKG_ENERGY_STATUS          0x00000611
 #define MSR_PKG_PERF_STATUS            0x00000613
 #define MSR_PKG_POWER_INFO             0x00000614
@@ -165,7 +203,8 @@
 #define MSR_PP1_POWER_LIMIT            0x00000640
 #define MSR_PP1_ENERGY_STATUS          0x00000641
 #define MSR_PP1_POLICY                 0x00000642
-
+#define MSR_CONFIG_TDP_NOMINAL         0x00000648
+#define MSR_TURBO_ACTIVATION_RATIO     0x0000064c
 #define MSR_CORE_C1_RES                        0x00000660
 #define MSR_IACORE_RATIOS              0x0000066a
 #define MSR_IACORE_TURBO_RATIOS                0x0000066c