We were not consistent with minimums reported in the physical device
properties.
Fixes a few CTS tests :
dEQP-VK.memory.requirements.dedicated_allocation.buffer.regular
dEQP-VK.memory.requirements.extended.buffer.regular
dEQP-VK.memory.requirements.core.buffer.regular
v2: Use define for the limit
v3: Rename define
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
a0de2e0090535b ("anv: increase minUniformBufferOffsetAlignment to 64")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4940>
*/
if (type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER ||
type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC)
- bind_range = align_u64(bind_range, ANV_UBO_BOUNDS_CHECK_ALIGNMENT);
+ bind_range = align_u64(bind_range, ANV_UBO_ALIGNMENT);
if (type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
* case of R32G32B32A32 which is 16 bytes.
*/
.minTexelBufferOffsetAlignment = 16,
- /* We need 16 for UBO block reads to work and 32 for push UBOs.
- * However, we use 64 here to avoid cache issues.
- */
- .minUniformBufferOffsetAlignment = 64,
+ .minUniformBufferOffsetAlignment = ANV_UBO_ALIGNMENT,
.minStorageBufferOffsetAlignment = 4,
.minTexelOffset = -8,
.maxTexelOffset = 7,
properties->robustStorageBufferAccessSizeAlignment =
ANV_SSBO_BOUNDS_CHECK_ALIGNMENT;
properties->robustUniformBufferAccessSizeAlignment =
- ANV_UBO_BOUNDS_CHECK_ALIGNMENT;
+ ANV_UBO_ALIGNMENT;
break;
}
/* Base alignment requirement of a cache line */
uint32_t alignment = 16;
- /* We need an alignment of 32 for pushing UBOs */
if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT)
- alignment = MAX2(alignment, 32);
+ alignment = MAX2(alignment, ANV_UBO_ALIGNMENT);
pMemoryRequirements->size = buffer->size;
pMemoryRequirements->alignment = alignment;
#define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
#define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
#define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
-#define ANV_UBO_BOUNDS_CHECK_ALIGNMENT 32
+/* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
+ * use 64 here to avoid cache issues. This could most likely bring it back to
+ * 32 if we had different virtual addresses for the different views on a given
+ * GEM object.
+ */
+#define ANV_UBO_ALIGNMENT 64
#define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
#define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
/* Align the range for consistency */
if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC)
- range = align_u32(range, ANV_UBO_BOUNDS_CHECK_ALIGNMENT);
+ range = align_u32(range, ANV_UBO_ALIGNMENT);
struct anv_address address =
anv_address_add(desc->buffer->address, offset);
uint32_t bound_range = MIN2(desc->range, desc->buffer->size - offset);
/* Align the range for consistency */
- bound_range = align_u32(bound_range, ANV_UBO_BOUNDS_CHECK_ALIGNMENT);
+ bound_range = align_u32(bound_range, ANV_UBO_ALIGNMENT);
return bound_range;
}