* Register usages:
*
* r5 has zero always
+ * r6 is used at memory configuration
* r7 has GPIO part1 base 0x11400000
* r8 has GPIO part2 base 0x11000000
*/
ldr r7, =S5PC210_GPIO_PART1_BASE
ldr r8, =S5PC210_GPIO_PART2_BASE
+#if 0
/* IO retension release */
ldr r0, =0x10020000
ldr r2, =(1 << 28)
ldr r3, =0x31A8
add r1, r0, r3
str r2, [r1]
+#endif
#ifdef CONFIG_PRELOADER
bl mem_ctrl_asm_init
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
str r1, [r0, #0x4]
-#if 1
+#if 0
ldr r0, =0x13800000 @ S5PC210_PA_UART
orr r0, r0, #0x20000 @ UART2
mov r1, #0x3
# S5PC210 loads at 0x02020000 (EVT0)
# S5PC210 loads at 0xxxxxxxxx (EVT1)
# Header (16 bytes) are added after more
-TEXT_BASE = 0x02028000
-TEXT_BASE16K_EVT0 = 0x0202c000
+TEXT_BASE = 0x02022000
+TEXT_BASE16K_EVT0 = 0x02026000
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot-onenand.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
SOBJS := lowlevel_init.o mem_setup.o
SOBJS += start.o _memcpy32.o
-#SOBJS += cache.o
COBJS += onenand_read.o
COBJS += onenand_boot.o
ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
# from SoC directory
-#$(obj)cache.S:
-# @rm -f $@
-# ln -s $(SRCTREE)/$(CPUDIR)/$(SOC)/cache.S $@
$(obj)mem_setup.S:
ln -sf $(SRCTREE)/board/$(BOARDDIR)/mem_setup.S $@