ASoC: SOF: Intel: hda: Add sof_tgl_ops for TGL platforms
authorRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Wed, 26 Aug 2020 18:45:31 +0000 (11:45 -0700)
committerMark Brown <broonie@kernel.org>
Thu, 27 Aug 2020 13:22:23 +0000 (14:22 +0100)
Separate the dsp ops for TGL ops to specify the use of ICCMAX
FW boot sequence in the run op. All other ops are identical.
Also separate the TGL descriptors into a separate file to make
it easier to follow.

Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20200826184532.1612070-8-ranjani.sridharan@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/Makefile
sound/soc/sof/intel/cnl.c
sound/soc/sof/intel/hda-ipc.h
sound/soc/sof/intel/hda.h
sound/soc/sof/intel/tgl.c [new file with mode: 0644]
sound/soc/sof/sof-pci-dev.c

index f7e9358f1f068d12e95124afd8f2fed2660a656c..72d85b25df7d4a8aad5f81694a66cd3c73aec0fa 100644 (file)
@@ -8,7 +8,7 @@ snd-sof-intel-ipc-objs := intel-ipc.o
 snd-sof-intel-hda-common-objs := hda.o hda-loader.o hda-stream.o hda-trace.o \
                                 hda-dsp.o hda-ipc.o hda-ctrl.o hda-pcm.o \
                                 hda-dai.o hda-bus.o \
-                                apl.o cnl.o
+                                apl.o cnl.o tgl.o
 snd-sof-intel-hda-common-$(CONFIG_SND_SOC_SOF_HDA_PROBES) += hda-compress.o
 
 snd-sof-intel-hda-objs := hda-codec.o
index 95234ae59e42b75744d7372b3978c2580bfadea2..70f14b2aa954024ba257cf2ef2fe2a715ca3f2c4 100644 (file)
@@ -29,7 +29,7 @@ static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
 static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
 
-static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
+irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
 {
        struct snd_sof_dev *sdev = context;
        u32 hipci;
@@ -163,8 +163,7 @@ static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
        return false;
 }
 
-static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
-                           struct snd_sof_ipc_msg *msg)
+int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
 {
        struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
        struct sof_ipc_cmd_hdr *hdr;
@@ -211,7 +210,7 @@ static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
        return 0;
 }
 
-static void cnl_ipc_dump(struct snd_sof_dev *sdev)
+void cnl_ipc_dump(struct snd_sof_dev *sdev)
 {
        u32 hipcctl;
        u32 hipcida;
@@ -369,22 +368,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
-const struct sof_intel_dsp_desc tgl_chip_info = {
-       /* Tigerlake */
-       .cores_num = 4,
-       .init_core_mask = 1,
-       .cores_mask = HDA_DSP_CORE_MASK(0),
-       .ipc_req = CNL_DSP_REG_HIPCIDR,
-       .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
-       .ipc_ack = CNL_DSP_REG_HIPCIDA,
-       .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
-       .ipc_ctl = CNL_DSP_REG_HIPCCTL,
-       .rom_init_timeout       = 300,
-       .ssp_count = ICL_SSP_COUNT,
-       .ssp_base_offset = CNL_SSP_BASE_OFFSET,
-};
-EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
-
 const struct sof_intel_dsp_desc ehl_chip_info = {
        /* Elkhartlake */
        .cores_num = 4,
index ade4c3191a39c924d108b526cfebda5a7bef85ab..10fbca5939dba63dd4f70cb97adab1670aaa5671 100644 (file)
@@ -48,4 +48,8 @@
 #define HDA_PM_PG_STREAMING    BIT(1)
 #define HDA_PM_PG_RSVD         BIT(0)
 
+irqreturn_t cnl_ipc_irq_thread(int irq, void *context);
+int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
+void cnl_ipc_dump(struct snd_sof_dev *sdev);
+
 #endif
index a2e6050f0ef063be4b8933f418461d897e739e81..5ee2f835405183ee9dd3a10567d44d7c555f9836 100644 (file)
@@ -733,6 +733,7 @@ extern struct snd_soc_dai_driver skl_dai[];
  */
 extern const struct snd_sof_dsp_ops sof_apl_ops;
 extern const struct snd_sof_dsp_ops sof_cnl_ops;
+extern const struct snd_sof_dsp_ops sof_tgl_ops;
 
 extern const struct sof_intel_dsp_desc apl_chip_info;
 extern const struct sof_intel_dsp_desc cnl_chip_info;
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
new file mode 100644 (file)
index 0000000..d0e84b7
--- /dev/null
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+//
+// Copyright(c) 2020 Intel Corporation. All rights reserved.
+//
+// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+//
+
+/*
+ * Hardware interface for audio DSP on Tigerlake.
+ */
+
+#include "../ops.h"
+#include "hda.h"
+#include "hda-ipc.h"
+#include "../sof-audio.h"
+
+static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
+       {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
+       {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
+       {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
+};
+
+/* Tigerlake ops */
+const struct snd_sof_dsp_ops sof_tgl_ops = {
+       /* probe and remove */
+       .probe          = hda_dsp_probe,
+       .remove         = hda_dsp_remove,
+
+       /* Register IO */
+       .write          = sof_io_write,
+       .read           = sof_io_read,
+       .write64        = sof_io_write64,
+       .read64         = sof_io_read64,
+
+       /* Block IO */
+       .block_read     = sof_block_read,
+       .block_write    = sof_block_write,
+
+       /* doorbell */
+       .irq_thread     = cnl_ipc_irq_thread,
+
+       /* ipc */
+       .send_msg       = cnl_ipc_send_msg,
+       .fw_ready       = sof_fw_ready,
+       .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
+       .get_window_offset = hda_dsp_ipc_get_window_offset,
+
+       .ipc_msg_data   = hda_ipc_msg_data,
+       .ipc_pcm_params = hda_ipc_pcm_params,
+
+       /* machine driver */
+       .machine_select = hda_machine_select,
+       .machine_register = sof_machine_register,
+       .machine_unregister = sof_machine_unregister,
+       .set_mach_params = hda_set_mach_params,
+
+       /* debug */
+       .debug_map      = tgl_dsp_debugfs,
+       .debug_map_count        = ARRAY_SIZE(tgl_dsp_debugfs),
+       .dbg_dump       = hda_dsp_dump,
+       .ipc_dump       = cnl_ipc_dump,
+
+       /* stream callbacks */
+       .pcm_open       = hda_dsp_pcm_open,
+       .pcm_close      = hda_dsp_pcm_close,
+       .pcm_hw_params  = hda_dsp_pcm_hw_params,
+       .pcm_hw_free    = hda_dsp_stream_hw_free,
+       .pcm_trigger    = hda_dsp_pcm_trigger,
+       .pcm_pointer    = hda_dsp_pcm_pointer,
+
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
+       /* probe callbacks */
+       .probe_assign   = hda_probe_compr_assign,
+       .probe_free     = hda_probe_compr_free,
+       .probe_set_params       = hda_probe_compr_set_params,
+       .probe_trigger  = hda_probe_compr_trigger,
+       .probe_pointer  = hda_probe_compr_pointer,
+#endif
+
+       /* firmware loading */
+       .load_firmware = snd_sof_load_firmware_raw,
+
+       /* pre/post fw run */
+       .pre_fw_run = hda_dsp_pre_fw_run,
+       .post_fw_run = hda_dsp_post_fw_run,
+
+       /* dsp core power up/down */
+       .core_power_up = hda_dsp_enable_core,
+       .core_power_down = hda_dsp_core_reset_power_down,
+
+       /* firmware run */
+       .run = hda_dsp_cl_boot_firmware_iccmax,
+
+       /* trace callback */
+       .trace_init = hda_dsp_trace_init,
+       .trace_release = hda_dsp_trace_release,
+       .trace_trigger = hda_dsp_trace_trigger,
+
+       /* DAI drivers */
+       .drv            = skl_dai,
+       .num_drv        = SOF_SKL_NUM_DAIS,
+
+       /* PM */
+       .suspend                = hda_dsp_suspend,
+       .resume                 = hda_dsp_resume,
+       .runtime_suspend        = hda_dsp_runtime_suspend,
+       .runtime_resume         = hda_dsp_runtime_resume,
+       .runtime_idle           = hda_dsp_runtime_idle,
+       .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
+       .set_power_state        = hda_dsp_set_power_state,
+
+       /* ALSA HW info flags */
+       .hw_info =      SNDRV_PCM_INFO_MMAP |
+                       SNDRV_PCM_INFO_MMAP_VALID |
+                       SNDRV_PCM_INFO_INTERLEAVED |
+                       SNDRV_PCM_INFO_PAUSE |
+                       SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
+
+       .arch_ops = &sof_xtensa_arch_ops,
+};
+EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
+
+const struct sof_intel_dsp_desc tgl_chip_info = {
+       /* Tigerlake */
+       .cores_num = 4,
+       .init_core_mask = 1,
+       .cores_mask = HDA_DSP_CORE_MASK(0),
+       .ipc_req = CNL_DSP_REG_HIPCIDR,
+       .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
+       .ipc_ack = CNL_DSP_REG_HIPCIDA,
+       .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
+       .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_init_timeout       = 300,
+       .ssp_count = ICL_SSP_COUNT,
+       .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+};
+EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
index 7b85c88cba9cecc5082369b424fc310630f52759..ec62d9337d6878bce6e3f6792c8c3c7bca8d8624 100644 (file)
@@ -221,7 +221,7 @@ static const struct sof_dev_desc tgl_desc = {
        .default_tplg_path = "intel/sof-tplg",
        .default_fw_filename = "sof-tgl.ri",
        .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
-       .ops = &sof_cnl_ops,
+       .ops = &sof_tgl_ops,
 };
 #endif