/* r5 has always zero */
mov r5, #0
- ldr r8, =S5P6442_GPIO_BASE
+ ldr r8, =S5P6442_GPIO_BASE @0xE0200000
/* IO retension release */
ldr r0, =S5P6442_OTHERS @0xE010E000
ldr r1, [r0]
- ldreq r2, =(1 << 31) @IO_RET_REL
- ldrne r2, =((1 << 31) | (1 << 29) | (1 << 28)) @ GPIO, UART_IO
+ ldr r2, =(1 << 31) @IO_RET_REL
orr r1, r1, r2
str r1, [r0]
str r5, [r0]
/* setting SRAM */
- ldr r0, =S5P6442_SROMC_BASE
+ ldr r0, =S5P6442_SROMC_BASE @0xE7000000
ldr r1, =0x9
str r1, [r0]
#endif
/* S5P6442 has 3 groups of interrupt sources */
ldr r0, =S5P6442_VIC0_BASE @0xE4000000
- ldr r1, =S5P6442_VIC1_BASE @0xE4000000
- ldr r2, =S5P6442_VIC2_BASE @0xE4000000
+ add r1, r0, #0x00100000
+ add r2, r0, #0x00200000
/* Disable all interrupts (VIC0, VIC1 and VIC2) */
mvn r3, #0x0
system_clock_init:
ldr r8, =S5P64XX_CLOCK_BASE @ 0xE0100000
- /* Set Clock divider */
- ldr r1, =0x10100000
- str r1, [r8, #0x300]
-
/* Set Lock Time */
ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
str r1, [r8, #0x000] @ APLL_LOCK
ldr r1, =0x1111 @ A, M, E, VPLL Muxing
str r1, [r8, #0x200] @ CLK_SRC0
+ /* Set Clock divider */
+ ldr r1, =0x10100000
+ str r1, [r8, #0x300]
+
/* wait at least 200us to stablize all clock */
mov r2, #0x10000
1: subs r2, r2, #1
mov r0, r8
ldr r1, =0x22222222
str r1, [r0, #0x0] @ GPA0_CON
- ldr r1, =0x00022222
+ ldr r1, =0x00000022
str r1, [r0, #0x20] @ GPA1_CON
mov pc, lr
str r1, [r6, #0x018] @ PHYCONTROL0
ldr r1, =0x00008044
str r1, [r6, #0x01C] @ PHYCONTROL1
- ldr r1, =0x0
- str r1, [r6, #0x020] @ PHYCONTROL2
/* DLL on */
ldr r1, =0x0014140a
ldr r1, =0x0014140b
str r1, [r6, #0x018] @ PHYCONTROL0
- /* Force value locking for DLL off */
- str r1, [r6, #0x018] @ PHYCONTROL0
-
- /* DLL off */
- ldr r1, =0x00141409
- str r1, [r6, #0x018] @ PHYCONTROL0
-
/* auto refresh off */
- ldr r1, =0x0f0010d0
+ ldr r1, =0x0f001090
str r1, [r6, #0x000] @ CONCONTROL
/*
str r1, [r6, #0x004] @ MEMCONTROL
/*
- * Note:
- * If Bank0 has OneDRAM we place it at 0x2800'0000
- * So finally Bank1 should address start at at 0x2000'0000
- */
- mov r4, #0x0
-
-#if 0
-swap_memory:
- /*
* Bank0
- * 0x30 -> 0x30000000
- * 0xf8 -> 0x37FFFFFF
+ * 0x20 -> 0x20000000
+ * 0xf0 -> 0x2FFFFFFF
* [15:12] 0: Linear
- * [11:8 ] 2: 9 bits
- * [ 7:4 ] 2: 14 bits
+ * [11:8 ] 3: 10 bits
+ * [ 7:4 ] 1: 13 bits
* [ 3:0 ] 2: 4 banks
*/
- ldr r1, =0x30f80222
- /* if r4 is 1, swap the bank */
- cmp r4, #0x1
- orreq r1, r1, #0x08000000
+ ldr r1, =0x20f00312
str r1, [r6, #0x008] @ MEMCONFIG0
/*
* Bank1
- * 0x38 -> 0x38000000
- * 0xf8 -> 0x3fFFFFFF
+ * 0x30 -> 0x30000000
+ * 0xf0 -> 0x3FFFFFFF
* [15:12] 0: Linear
* [11:8 ] 2: 9 bits
* [ 7:4 ] 2: 14 bits
* [ 3:0 ] 2: 4 banks
*/
- ldr r1, =0x38f80222
- /* if r4 is 1, swap the bank */
- cmp r4, #0x1
- biceq r1, r1, #0x08000000
+ ldr r1, =0x30f00222
str r1, [r6, #0x00c] @ MEMCONFIG1
- ldr r1, =0x20000000
+ ldr r1, =0xf0000000
str r1, [r6, #0x014] @ PRECHCONFIG
-#endif
/*
* FIXME: Please verify these values
ldr r1, =0x0000040e
str r1, [r6, #0x030] @ TIMINGAREF
- /* 166 MHz */
+ /* 133 MHz */
ldr r1, =0x0c233286
str r1, [r6, #0x034] @ TIMINGROW
- /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+ /* t_wtr=1 t_wr=2 t_rtp=1 cl=3 wl=0 rl=5 */
ldr r1, =0x12130005
str r1, [r6, #0x038] @ TIMINGDATA
- /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
- ldr r1, =0x0e120222
+ /* t_faw=0xe t_xsr=0x10 t_xp=2 t_cke=2 t_mrd=2 */
+ ldr r1, =0x0e100222
str r1, [r6, #0x03C] @ TIMINGPOWER
/* chip0 Deselect */
ldr r1, =0x00000032
str r1, [r6, #0x010] @ DIRECTCMD
- /* chip1 Deselect */
- ldr r1, =0x07100000
- str r1, [r6, #0x010] @ DIRECTCMD
-
- /* chip1 PALL */
- ldr r1, =0x01100000
- str r1, [r6, #0x010] @ DIRECTCMD
-
- /* chip1 REFA */
- ldr r1, =0x05100000
- str r1, [r6, #0x010] @ DIRECTCMD
- /* chip1 REFA */
- str r1, [r6, #0x010] @ DIRECTCMD
-
- /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
- ldr r1, =0x00100032
- str r1, [r6, #0x010] @ DIRECTCMD
-
/* auto refresh on */
- ldr r1, =0x0f0010f0
+ ldr r1, =0x0f0010b0
str r1, [r6, #0x000] @ CONCONTROL
/* PwrdnConfig */
str r1, [r6, #0x028] @ PWRDNCONFIG
/* BL%LE %LONG */
- ldr r1, =0x00212100
+ ldr r1, =0x00202100
str r1, [r6, #0x004] @ MEMCONTROL
-#if 0
- /* Try to test memory area */
- cmp r4, #0x1
- beq 1f
-
- mov r4, #0x1
- ldr r1, =0x37ffff00
- str r4, [r1]
- str r4, [r1, #0x4] @ dummy write
- ldr r0, [r1]
- cmp r0, r4
- bne swap_memory
-#endif
-
-1:
mov pc, lr
.ltorg