arm64: dts: mediatek: add mmc support for mt8365 SoC

There are three ports of MSDC (MMC and SD Controller), which are:
- MSDC0: EMMC5.1
- MSDC1: SD3.0/SDIO3.0
- MSDC2: SDIO3.0+

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-8-0003e80e0095@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 713c560..2a56997 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -388,6 +388,45 @@
                        };
                };
 
+               mmc0: mmc@11230000 {
+                       compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+                       reg = <0 0x11230000 0 0x1000>,
+                             <0 0x11cd0000 0 0x1000>;
+                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+                                <&infracfg CLK_IFR_MSDC0_HCLK>,
+                                <&infracfg CLK_IFR_MSDC0_SRC>;
+                       clock-names = "source", "hclk", "source_cg";
+                       status = "disabled";
+               };
+
+               mmc1: mmc@11240000 {
+                       compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+                       reg = <0 0x11240000 0 0x1000>,
+                             <0 0x11c90000 0 0x1000>;
+                       interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+                                <&infracfg CLK_IFR_MSDC1_HCLK>,
+                                <&infracfg CLK_IFR_MSDC1_SRC>;
+                       clock-names = "source", "hclk", "source_cg";
+                       status = "disabled";
+               };
+
+               mmc2: mmc@11250000 {
+                       compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+                       reg = <0 0x11250000 0 0x1000>,
+                             <0 0x11c60000 0 0x1000>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
+                                <&infracfg CLK_IFR_MSDC2_HCLK>,
+                                <&infracfg CLK_IFR_MSDC2_SRC>,
+                                <&infracfg CLK_IFR_MSDC2_BK>,
+                                <&infracfg CLK_IFR_AP_MSDC0>;
+                       clock-names = "source", "hclk", "source_cg",
+                                     "bus_clk", "sys_cg";
+                       status = "disabled";
+               };
+
                u3phy: t-phy@11cc0000 {
                        compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
                        #address-cells = <1>;