return NULL;
}
+struct radv_shader_part *
+radv_create_tcs_epilog(struct radv_device *device, const struct radv_tcs_epilog_key *key)
+{
+ struct radv_shader_part *epilog;
+ struct radv_shader_args args = {0};
+ struct radv_nir_compiler_options options = {0};
+ radv_fill_nir_compiler_options(&options, device, NULL, false,
+ device->instance->debug_flags & RADV_DEBUG_DUMP_EPILOGS, false,
+ device->instance->debug_flags & RADV_DEBUG_HANG, false);
+
+ struct radv_shader_info info = {0};
+ info.stage = MESA_SHADER_TESS_CTRL;
+ info.wave_size = device->physical_device->ge_wave_size;
+ info.workgroup_size = 64;
+
+ radv_declare_tcs_epilog_args(device, key, &args);
+
+#ifdef LLVM_AVAILABLE
+ if (options.dump_shader || options.record_ir)
+ ac_init_llvm_once();
+#endif
+
+ struct radv_shader_part_binary *binary = NULL;
+ struct aco_shader_info ac_info;
+ struct aco_tcs_epilog_info ac_epilog_info;
+ struct aco_compiler_options ac_opts;
+ radv_aco_convert_shader_info(&ac_info, &info, &args, &options.key, options.info->gfx_level);
+ radv_aco_convert_opts(&ac_opts, &options, &args);
+ radv_aco_convert_tcs_epilog_key(&ac_epilog_info, key, &args);
+ aco_compile_tcs_epilog(&ac_opts, &ac_info, &ac_epilog_info, &args.ac, &radv_aco_build_shader_part, (void **)&binary);
+
+ epilog = radv_shader_part_create(device, binary, info.wave_size);
+ if (!epilog)
+ goto fail;
+
+ if (options.dump_shader) {
+ fprintf(stderr, "TCS epilog");
+ fprintf(stderr, "\ndisasm:\n%s\n", epilog->disasm_string);
+ }
+
+ free(binary);
+ return epilog;
+
+fail:
+ free(binary);
+ return NULL;
+}
+
void
radv_shader_part_destroy(struct radv_device *device, struct radv_shader_part *shader_part)
{
struct radv_shader_part *radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_key *key,
struct radv_shader_part_binary **binary_out);
+struct radv_shader_part *radv_create_tcs_epilog(struct radv_device *device, const struct radv_tcs_epilog_key *key);
+
void radv_shader_part_destroy(struct radv_device *device, struct radv_shader_part *shader_part);
uint64_t radv_shader_get_va(const struct radv_shader *shader);
ac_add_arg(&args->ac, AC_ARG_VGPR, 4, AC_ARG_FLOAT, &args->ps_epilog_inputs[i]);
}
}
+
+void
+radv_declare_tcs_epilog_args(const struct radv_device *device, const struct radv_tcs_epilog_key *key,
+ struct radv_shader_args *args)
+{
+ const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
+
+ radv_init_shader_args(device, MESA_SHADER_TESS_CTRL, args);
+
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 2, AC_ARG_CONST_DESC_PTR, &args->ac.ring_offsets);
+
+ if (gfx_level < GFX11)
+ ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
+
+ /* TODO: declare other arguments. */
+}
void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
struct radv_shader_args *args);
+void radv_declare_tcs_epilog_args(const struct radv_device *device, const struct radv_tcs_epilog_key *key,
+ struct radv_shader_args *args);
+
void radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_args *args);
#endif