; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[0]
-; CHECK-NEXT: mov w9, #8969
-; CHECK-NEXT: movk w9, #22765, lsl #16
+; CHECK-NEXT: mov w9, #55879
+; CHECK-NEXT: movk w9, #689, lsl #16
; CHECK-NEXT: umov w10, v0.h[1]
-; CHECK-NEXT: mov w12, #16913
-; CHECK-NEXT: mov w13, #95
-; CHECK-NEXT: movk w12, #8456, lsl #16
+; CHECK-NEXT: mov w11, #33826
+; CHECK-NEXT: mov w12, #95
+; CHECK-NEXT: movk w11, #528, lsl #16
+; CHECK-NEXT: umov w13, v0.h[2]
; CHECK-NEXT: umull x9, w8, w9
-; CHECK-NEXT: ubfx w14, w10, #2, #14
+; CHECK-NEXT: umull x11, w10, w11
; CHECK-NEXT: lsr x9, x9, #32
-; CHECK-NEXT: sub w11, w8, w9
-; CHECK-NEXT: umull x12, w14, w12
-; CHECK-NEXT: add w9, w9, w11, lsr #1
-; CHECK-NEXT: umov w11, v0.h[2]
-; CHECK-NEXT: lsr w9, w9, #6
-; CHECK-NEXT: lsr x12, x12, #34
-; CHECK-NEXT: msub w8, w9, w13, w8
-; CHECK-NEXT: mov w9, #33437
-; CHECK-NEXT: movk w9, #21399, lsl #16
-; CHECK-NEXT: mov w13, #124
-; CHECK-NEXT: umull x9, w11, w9
-; CHECK-NEXT: msub w10, w12, w13, w10
-; CHECK-NEXT: umov w12, v0.h[3]
+; CHECK-NEXT: lsr x11, x11, #32
+; CHECK-NEXT: msub w8, w9, w12, w8
+; CHECK-NEXT: mov w9, #48149
+; CHECK-NEXT: movk w9, #668, lsl #16
+; CHECK-NEXT: mov w12, #124
+; CHECK-NEXT: umull x9, w13, w9
+; CHECK-NEXT: msub w10, w11, w12, w10
+; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov w13, #2287
-; CHECK-NEXT: lsr x8, x9, #37
+; CHECK-NEXT: mov w12, #22281
+; CHECK-NEXT: lsr x8, x9, #32
; CHECK-NEXT: mov w9, #98
-; CHECK-NEXT: movk w13, #16727, lsl #16
-; CHECK-NEXT: msub w8, w8, w9, w11
+; CHECK-NEXT: movk w12, #65, lsl #16
+; CHECK-NEXT: msub w8, w8, w9, w13
; CHECK-NEXT: mov v0.h[1], w10
-; CHECK-NEXT: umull x9, w12, w13
+; CHECK-NEXT: umull x9, w11, w12
; CHECK-NEXT: mov w10, #1003
-; CHECK-NEXT: lsr x9, x9, #40
+; CHECK-NEXT: lsr x9, x9, #32
; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: msub w8, w9, w10, w12
+; CHECK-NEXT: msub w8, w9, w10, w11
; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
; CHECK-LABEL: fold_urem_vec_2:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: umov w10, v0.h[0]
-; CHECK-NEXT: mov w8, #8969
-; CHECK-NEXT: umov w9, v0.h[1]
-; CHECK-NEXT: movk w8, #22765, lsl #16
-; CHECK-NEXT: umov w15, v0.h[2]
-; CHECK-NEXT: umov w16, v0.h[3]
-; CHECK-NEXT: umull x12, w10, w8
-; CHECK-NEXT: umull x11, w9, w8
-; CHECK-NEXT: lsr x12, x12, #32
+; CHECK-NEXT: umov w8, v0.h[0]
+; CHECK-NEXT: mov w9, #55879
+; CHECK-NEXT: movk w9, #689, lsl #16
+; CHECK-NEXT: umov w10, v0.h[1]
+; CHECK-NEXT: mov w12, #95
+; CHECK-NEXT: umov w13, v0.h[2]
+; CHECK-NEXT: umull x11, w8, w9
+; CHECK-NEXT: umull x14, w10, w9
; CHECK-NEXT: lsr x11, x11, #32
-; CHECK-NEXT: sub w14, w10, w12
-; CHECK-NEXT: sub w13, w9, w11
-; CHECK-NEXT: add w12, w12, w14, lsr #1
-; CHECK-NEXT: umull x14, w15, w8
-; CHECK-NEXT: add w11, w11, w13, lsr #1
-; CHECK-NEXT: mov w13, #95
-; CHECK-NEXT: lsr w12, w12, #6
-; CHECK-NEXT: lsr w11, w11, #6
-; CHECK-NEXT: umull x8, w16, w8
-; CHECK-NEXT: msub w10, w12, w13, w10
-; CHECK-NEXT: lsr x12, x14, #32
-; CHECK-NEXT: msub w9, w11, w13, w9
-; CHECK-NEXT: sub w11, w15, w12
-; CHECK-NEXT: lsr x8, x8, #32
-; CHECK-NEXT: fmov s0, w10
-; CHECK-NEXT: add w10, w12, w11, lsr #1
-; CHECK-NEXT: lsr w10, w10, #6
-; CHECK-NEXT: sub w11, w16, w8
-; CHECK-NEXT: mov v0.h[1], w9
-; CHECK-NEXT: msub w9, w10, w13, w15
-; CHECK-NEXT: add w8, w8, w11, lsr #1
-; CHECK-NEXT: lsr w8, w8, #6
-; CHECK-NEXT: mov v0.h[2], w9
-; CHECK-NEXT: msub w8, w8, w13, w16
+; CHECK-NEXT: msub w8, w11, w12, w8
+; CHECK-NEXT: lsr x11, x14, #32
+; CHECK-NEXT: umull x14, w13, w9
+; CHECK-NEXT: msub w10, w11, w12, w10
+; CHECK-NEXT: umov w11, v0.h[3]
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: lsr x8, x14, #32
+; CHECK-NEXT: msub w8, w8, w12, w13
+; CHECK-NEXT: mov v0.h[1], w10
+; CHECK-NEXT: umull x9, w11, w9
+; CHECK-NEXT: lsr x9, x9, #32
+; CHECK-NEXT: mov v0.h[2], w8
+; CHECK-NEXT: msub w8, w9, w12, w11
; CHECK-NEXT: mov v0.h[3], w8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
; CHECK-LABEL: combine_urem_udiv:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: umov w9, v0.h[0]
-; CHECK-NEXT: mov w8, #8969
-; CHECK-NEXT: movk w8, #22765, lsl #16
+; CHECK-NEXT: umov w8, v0.h[0]
+; CHECK-NEXT: mov w9, #55879
+; CHECK-NEXT: movk w9, #689, lsl #16
; CHECK-NEXT: umov w10, v0.h[1]
-; CHECK-NEXT: umov w11, v0.h[2]
-; CHECK-NEXT: mov w15, #95
-; CHECK-NEXT: umov w13, v0.h[3]
-; CHECK-NEXT: umull x12, w9, w8
-; CHECK-NEXT: umull x14, w10, w8
-; CHECK-NEXT: lsr x12, x12, #32
-; CHECK-NEXT: umull x17, w11, w8
-; CHECK-NEXT: sub w16, w9, w12
-; CHECK-NEXT: lsr x14, x14, #32
-; CHECK-NEXT: lsr x17, x17, #32
-; CHECK-NEXT: umull x8, w13, w8
-; CHECK-NEXT: add w12, w12, w16, lsr #1
-; CHECK-NEXT: sub w16, w10, w14
-; CHECK-NEXT: lsr w12, w12, #6
+; CHECK-NEXT: mov w12, #95
+; CHECK-NEXT: umov w14, v0.h[2]
+; CHECK-NEXT: umov w15, v0.h[3]
+; CHECK-NEXT: umull x11, w8, w9
+; CHECK-NEXT: umull x13, w10, w9
+; CHECK-NEXT: lsr x11, x11, #32
+; CHECK-NEXT: lsr x13, x13, #32
+; CHECK-NEXT: msub w8, w11, w12, w8
+; CHECK-NEXT: msub w10, w13, w12, w10
+; CHECK-NEXT: fmov s1, w11
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: umull x8, w14, w9
+; CHECK-NEXT: umull x9, w15, w9
; CHECK-NEXT: lsr x8, x8, #32
-; CHECK-NEXT: add w14, w14, w16, lsr #1
-; CHECK-NEXT: sub w16, w11, w17
-; CHECK-NEXT: msub w9, w12, w15, w9
-; CHECK-NEXT: lsr w14, w14, #6
-; CHECK-NEXT: add w16, w17, w16, lsr #1
-; CHECK-NEXT: fmov s1, w12
-; CHECK-NEXT: msub w10, w14, w15, w10
-; CHECK-NEXT: sub w17, w13, w8
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: lsr w9, w16, #6
-; CHECK-NEXT: mov v1.h[1], w14
-; CHECK-NEXT: add w8, w8, w17, lsr #1
-; CHECK-NEXT: msub w11, w9, w15, w11
-; CHECK-NEXT: lsr w8, w8, #6
; CHECK-NEXT: mov v0.h[1], w10
-; CHECK-NEXT: msub w10, w8, w15, w13
-; CHECK-NEXT: mov v1.h[2], w9
-; CHECK-NEXT: mov v0.h[2], w11
-; CHECK-NEXT: mov v1.h[3], w8
-; CHECK-NEXT: mov v0.h[3], w10
+; CHECK-NEXT: lsr x9, x9, #32
+; CHECK-NEXT: msub w10, w8, w12, w14
+; CHECK-NEXT: mov v1.h[1], w13
+; CHECK-NEXT: msub w11, w9, w12, w15
+; CHECK-NEXT: mov v0.h[2], w10
+; CHECK-NEXT: mov v1.h[2], w8
+; CHECK-NEXT: mov v0.h[3], w11
+; CHECK-NEXT: mov v1.h[3], w9
; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
; CHECK-LABEL: dont_fold_urem_power_of_two:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: umov w10, v0.h[0]
-; CHECK-NEXT: umov w9, v0.h[3]
-; CHECK-NEXT: mov w8, #8969
+; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w11, v0.h[1]
-; CHECK-NEXT: movk w8, #22765, lsl #16
-; CHECK-NEXT: and w10, w10, #0x3f
-; CHECK-NEXT: umull x8, w9, w8
-; CHECK-NEXT: and w11, w11, #0x1f
+; CHECK-NEXT: umov w10, v0.h[3]
+; CHECK-NEXT: mov w8, #55879
+; CHECK-NEXT: movk w8, #689, lsl #16
+; CHECK-NEXT: and w9, w9, #0x3f
+; CHECK-NEXT: umull x8, w10, w8
+; CHECK-NEXT: fmov s1, w9
+; CHECK-NEXT: and w9, w11, #0x1f
+; CHECK-NEXT: umov w11, v0.h[2]
; CHECK-NEXT: lsr x8, x8, #32
-; CHECK-NEXT: fmov s1, w10
-; CHECK-NEXT: umov w10, v0.h[2]
-; CHECK-NEXT: sub w12, w9, w8
-; CHECK-NEXT: mov v1.h[1], w11
-; CHECK-NEXT: add w8, w8, w12, lsr #1
-; CHECK-NEXT: and w10, w10, #0x7
-; CHECK-NEXT: lsr w8, w8, #6
-; CHECK-NEXT: mov w11, #95
-; CHECK-NEXT: msub w8, w8, w11, w9
-; CHECK-NEXT: mov v1.h[2], w10
+; CHECK-NEXT: mov v1.h[1], w9
+; CHECK-NEXT: mov w9, #95
+; CHECK-NEXT: and w11, w11, #0x7
+; CHECK-NEXT: msub w8, w8, w9, w10
+; CHECK-NEXT: mov v1.h[2], w11
; CHECK-NEXT: mov v1.h[3], w8
; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: ret
; CHECK-LABEL: dont_fold_srem_one:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: umov w9, v0.h[1]
-; CHECK-NEXT: mov w8, #30865
-; CHECK-NEXT: movk w8, #51306, lsl #16
-; CHECK-NEXT: umov w11, v0.h[2]
+; CHECK-NEXT: umov w8, v0.h[1]
+; CHECK-NEXT: mov w9, #13629
+; CHECK-NEXT: movk w9, #100, lsl #16
+; CHECK-NEXT: umov w10, v0.h[2]
+; CHECK-NEXT: mov w11, #25645
; CHECK-NEXT: mov w12, #654
+; CHECK-NEXT: movk w11, #2849, lsl #16
; CHECK-NEXT: movi d1, #0000000000000000
-; CHECK-NEXT: mov w13, #47143
-; CHECK-NEXT: ubfx w10, w9, #1, #15
-; CHECK-NEXT: movk w13, #24749, lsl #16
-; CHECK-NEXT: umull x8, w10, w8
-; CHECK-NEXT: mov w10, #17097
-; CHECK-NEXT: movk w10, #45590, lsl #16
-; CHECK-NEXT: lsr x8, x8, #40
-; CHECK-NEXT: umull x10, w11, w10
-; CHECK-NEXT: msub w8, w8, w12, w9
+; CHECK-NEXT: umull x9, w8, w9
+; CHECK-NEXT: mov w13, #5560
+; CHECK-NEXT: umull x11, w10, w11
+; CHECK-NEXT: movk w13, #12, lsl #16
+; CHECK-NEXT: lsr x9, x9, #32
+; CHECK-NEXT: lsr x11, x11, #32
+; CHECK-NEXT: msub w8, w9, w12, w8
; CHECK-NEXT: umov w9, v0.h[3]
-; CHECK-NEXT: lsr x10, x10, #36
; CHECK-NEXT: mov w12, #23
-; CHECK-NEXT: msub w10, w10, w12, w11
+; CHECK-NEXT: msub w10, w11, w12, w10
; CHECK-NEXT: mov w11, #5423
; CHECK-NEXT: mov v1.h[1], w8
; CHECK-NEXT: umull x8, w9, w13
-; CHECK-NEXT: lsr x8, x8, #43
+; CHECK-NEXT: lsr x8, x8, #32
; CHECK-NEXT: mov v1.h[2], w10
; CHECK-NEXT: msub w8, w8, w11, w9
; CHECK-NEXT: mov v1.h[3], w8
define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; P9LE-LABEL: fold_urem_vec_1:
; P9LE: # %bb.0:
-; P9LE-NEXT: li r3, 4
-; P9LE-NEXT: lis r4, 21399
-; P9LE-NEXT: lis r5, 8456
+; P9LE-NEXT: li r3, 0
+; P9LE-NEXT: lis r4, 689
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: ori r4, r4, 33437
-; P9LE-NEXT: ori r5, r5, 16913
+; P9LE-NEXT: ori r4, r4, 55879
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: srwi r4, r4, 5
-; P9LE-NEXT: mulli r4, r4, 98
+; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4
-; P9LE-NEXT: lis r4, 16727
+; P9LE-NEXT: lis r4, 528
; P9LE-NEXT: mtvsrd v3, r3
-; P9LE-NEXT: li r3, 6
-; P9LE-NEXT: ori r4, r4, 2287
+; P9LE-NEXT: li r3, 2
+; P9LE-NEXT: ori r4, r4, 33826
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: srwi r4, r4, 8
-; P9LE-NEXT: mulli r4, r4, 1003
+; P9LE-NEXT: mulli r4, r4, 124
; P9LE-NEXT: sub r3, r3, r4
+; P9LE-NEXT: lis r4, 668
; P9LE-NEXT: mtvsrd v4, r3
-; P9LE-NEXT: li r3, 2
+; P9LE-NEXT: li r3, 4
+; P9LE-NEXT: ori r4, r4, 48149
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
-; P9LE-NEXT: clrlwi r4, r3, 16
-; P9LE-NEXT: rlwinm r3, r3, 30, 18, 31
-; P9LE-NEXT: mulhwu r3, r3, r5
-; P9LE-NEXT: srwi r3, r3, 2
-; P9LE-NEXT: mulli r3, r3, 124
-; P9LE-NEXT: sub r3, r4, r3
-; P9LE-NEXT: lis r4, 22765
+; P9LE-NEXT: clrlwi r3, r3, 16
+; P9LE-NEXT: mulhwu r4, r3, r4
+; P9LE-NEXT: mulli r4, r4, 98
+; P9LE-NEXT: sub r3, r3, r4
+; P9LE-NEXT: lis r4, 65
; P9LE-NEXT: mtvsrd v4, r3
-; P9LE-NEXT: li r3, 0
-; P9LE-NEXT: ori r4, r4, 8969
+; P9LE-NEXT: li r3, 6
+; P9LE-NEXT: ori r4, r4, 22281
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: sub r5, r3, r4
-; P9LE-NEXT: srwi r5, r5, 1
-; P9LE-NEXT: add r4, r5, r4
-; P9LE-NEXT: srwi r4, r4, 6
-; P9LE-NEXT: mulli r4, r4, 95
+; P9LE-NEXT: mulli r4, r4, 1003
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3
-; P9LE-NEXT: vmrghh v2, v4, v2
-; P9LE-NEXT: xxmrglw v2, v3, v2
+; P9LE-NEXT: vmrghh v2, v2, v4
+; P9LE-NEXT: xxmrglw v2, v2, v3
; P9LE-NEXT: blr
;
; P9BE-LABEL: fold_urem_vec_1:
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
-; P9BE-NEXT: lis r4, 16727
-; P9BE-NEXT: lis r5, 8456
+; P9BE-NEXT: lis r4, 65
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: ori r4, r4, 2287
-; P9BE-NEXT: ori r5, r5, 16913
+; P9BE-NEXT: ori r4, r4, 22281
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: srwi r4, r4, 8
; P9BE-NEXT: mulli r4, r4, 1003
; P9BE-NEXT: sub r3, r3, r4
-; P9BE-NEXT: lis r4, 21399
+; P9BE-NEXT: lis r4, 668
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 4
-; P9BE-NEXT: ori r4, r4, 33437
+; P9BE-NEXT: ori r4, r4, 48149
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: srwi r4, r4, 5
; P9BE-NEXT: mulli r4, r4, 98
; P9BE-NEXT: sub r3, r3, r4
+; P9BE-NEXT: lis r4, 528
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
+; P9BE-NEXT: ori r4, r4, 33826
; P9BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
; P9BE-NEXT: lxv vs2, 0(r3)
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: clrlwi r4, r3, 16
-; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: xxperm vs0, vs1, vs2
-; P9BE-NEXT: mulhwu r3, r3, r5
-; P9BE-NEXT: srwi r3, r3, 2
-; P9BE-NEXT: mulli r3, r3, 124
-; P9BE-NEXT: sub r3, r4, r3
-; P9BE-NEXT: lis r4, 22765
+; P9BE-NEXT: mulhwu r4, r3, r4
+; P9BE-NEXT: mulli r4, r4, 124
+; P9BE-NEXT: sub r3, r3, r4
+; P9BE-NEXT: lis r4, 689
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: li r3, 0
-; P9BE-NEXT: ori r4, r4, 8969
+; P9BE-NEXT: ori r4, r4, 55879
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: sub r5, r3, r4
-; P9BE-NEXT: srwi r5, r5, 1
-; P9BE-NEXT: add r4, r5, r4
-; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtfprwz f3, r3
; P8LE-LABEL: fold_urem_vec_1:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r3, 22765
-; P8LE-NEXT: lis r7, 21399
-; P8LE-NEXT: lis r9, 16727
-; P8LE-NEXT: lis r10, 8456
-; P8LE-NEXT: ori r3, r3, 8969
-; P8LE-NEXT: ori r7, r7, 33437
-; P8LE-NEXT: ori r9, r9, 2287
-; P8LE-NEXT: ori r10, r10, 16913
+; P8LE-NEXT: lis r3, 689
+; P8LE-NEXT: lis r8, 528
+; P8LE-NEXT: lis r9, 668
+; P8LE-NEXT: lis r10, 65
+; P8LE-NEXT: ori r3, r3, 55879
+; P8LE-NEXT: ori r8, r8, 33826
+; P8LE-NEXT: ori r9, r9, 48149
+; P8LE-NEXT: ori r10, r10, 22281
; P8LE-NEXT: mffprd r4, f0
-; P8LE-NEXT: clrldi r6, r4, 48
-; P8LE-NEXT: rldicl r5, r4, 32, 48
-; P8LE-NEXT: clrlwi r6, r6, 16
-; P8LE-NEXT: rldicl r8, r4, 16, 48
+; P8LE-NEXT: clrldi r5, r4, 48
+; P8LE-NEXT: rldicl r6, r4, 48, 48
+; P8LE-NEXT: rldicl r7, r4, 32, 48
+; P8LE-NEXT: rldicl r4, r4, 16, 48
; P8LE-NEXT: clrlwi r5, r5, 16
-; P8LE-NEXT: mulhwu r3, r6, r3
-; P8LE-NEXT: rldicl r4, r4, 48, 48
-; P8LE-NEXT: clrlwi r8, r8, 16
-; P8LE-NEXT: rlwinm r11, r4, 30, 18, 31
-; P8LE-NEXT: mulhwu r7, r5, r7
+; P8LE-NEXT: clrlwi r6, r6, 16
+; P8LE-NEXT: mulhwu r3, r5, r3
+; P8LE-NEXT: clrlwi r7, r7, 16
; P8LE-NEXT: clrlwi r4, r4, 16
-; P8LE-NEXT: mulhwu r9, r8, r9
-; P8LE-NEXT: mulhwu r10, r11, r10
-; P8LE-NEXT: sub r11, r6, r3
-; P8LE-NEXT: srwi r11, r11, 1
-; P8LE-NEXT: srwi r7, r7, 5
-; P8LE-NEXT: add r3, r11, r3
-; P8LE-NEXT: srwi r9, r9, 8
-; P8LE-NEXT: srwi r10, r10, 2
-; P8LE-NEXT: srwi r3, r3, 6
-; P8LE-NEXT: mulli r7, r7, 98
-; P8LE-NEXT: mulli r9, r9, 1003
+; P8LE-NEXT: mulhwu r8, r6, r8
+; P8LE-NEXT: mulhwu r9, r7, r9
+; P8LE-NEXT: mulhwu r10, r4, r10
; P8LE-NEXT: mulli r3, r3, 95
-; P8LE-NEXT: mulli r10, r10, 124
-; P8LE-NEXT: sub r5, r5, r7
-; P8LE-NEXT: sub r7, r8, r9
-; P8LE-NEXT: sub r3, r6, r3
-; P8LE-NEXT: mtvsrd v2, r5
+; P8LE-NEXT: mulli r8, r8, 124
+; P8LE-NEXT: mulli r9, r9, 98
+; P8LE-NEXT: mulli r10, r10, 1003
+; P8LE-NEXT: sub r3, r5, r3
+; P8LE-NEXT: sub r5, r6, r8
+; P8LE-NEXT: mtvsrd v2, r3
+; P8LE-NEXT: sub r3, r7, r9
; P8LE-NEXT: sub r4, r4, r10
-; P8LE-NEXT: mtvsrd v3, r7
+; P8LE-NEXT: mtvsrd v3, r5
; P8LE-NEXT: mtvsrd v4, r3
; P8LE-NEXT: mtvsrd v5, r4
; P8LE-NEXT: vmrghh v2, v3, v2
; P8LE-NEXT: vmrghh v3, v5, v4
-; P8LE-NEXT: xxmrglw v2, v2, v3
+; P8LE-NEXT: xxmrglw v2, v3, v2
; P8LE-NEXT: blr
;
; P8BE-LABEL: fold_urem_vec_1:
; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2
-; P8BE-NEXT: lis r3, 22765
-; P8BE-NEXT: lis r7, 16727
-; P8BE-NEXT: lis r9, 21399
-; P8BE-NEXT: lis r10, 8456
-; P8BE-NEXT: ori r3, r3, 8969
-; P8BE-NEXT: ori r7, r7, 2287
-; P8BE-NEXT: ori r9, r9, 33437
-; P8BE-NEXT: ori r10, r10, 16913
-; P8BE-NEXT: rldicl r6, r4, 16, 48
+; P8BE-NEXT: lis r3, 65
+; P8BE-NEXT: lis r8, 668
+; P8BE-NEXT: lis r9, 528
+; P8BE-NEXT: lis r10, 689
+; P8BE-NEXT: ori r3, r3, 22281
+; P8BE-NEXT: ori r8, r8, 48149
+; P8BE-NEXT: ori r9, r9, 33826
+; P8BE-NEXT: ori r10, r10, 55879
; P8BE-NEXT: clrldi r5, r4, 48
-; P8BE-NEXT: clrlwi r6, r6, 16
+; P8BE-NEXT: rldicl r6, r4, 48, 48
; P8BE-NEXT: clrlwi r5, r5, 16
-; P8BE-NEXT: mulhwu r3, r6, r3
-; P8BE-NEXT: rldicl r8, r4, 48, 48
-; P8BE-NEXT: mulhwu r7, r5, r7
-; P8BE-NEXT: rldicl r4, r4, 32, 48
-; P8BE-NEXT: clrlwi r8, r8, 16
-; P8BE-NEXT: rlwinm r11, r4, 30, 18, 31
-; P8BE-NEXT: mulhwu r9, r8, r9
+; P8BE-NEXT: rldicl r7, r4, 32, 48
+; P8BE-NEXT: clrlwi r6, r6, 16
+; P8BE-NEXT: rldicl r4, r4, 16, 48
+; P8BE-NEXT: mulhwu r3, r5, r3
+; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: clrlwi r4, r4, 16
-; P8BE-NEXT: mulhwu r10, r11, r10
-; P8BE-NEXT: sub r11, r6, r3
-; P8BE-NEXT: srwi r7, r7, 8
-; P8BE-NEXT: srwi r11, r11, 1
-; P8BE-NEXT: add r3, r11, r3
-; P8BE-NEXT: mulli r7, r7, 1003
-; P8BE-NEXT: srwi r9, r9, 5
-; P8BE-NEXT: srwi r3, r3, 6
-; P8BE-NEXT: srwi r10, r10, 2
-; P8BE-NEXT: mulli r9, r9, 98
-; P8BE-NEXT: mulli r3, r3, 95
-; P8BE-NEXT: mulli r10, r10, 124
-; P8BE-NEXT: sub r5, r5, r7
-; P8BE-NEXT: addis r7, r2, .LCPI0_0@toc@ha
-; P8BE-NEXT: mtvsrwz v2, r5
-; P8BE-NEXT: addi r5, r7, .LCPI0_0@toc@l
-; P8BE-NEXT: sub r8, r8, r9
-; P8BE-NEXT: lxvw4x v3, 0, r5
-; P8BE-NEXT: sub r3, r6, r3
+; P8BE-NEXT: mulhwu r8, r6, r8
+; P8BE-NEXT: mulhwu r9, r7, r9
+; P8BE-NEXT: mulhwu r10, r4, r10
+; P8BE-NEXT: mulli r3, r3, 1003
+; P8BE-NEXT: mulli r8, r8, 98
+; P8BE-NEXT: mulli r9, r9, 124
+; P8BE-NEXT: mulli r10, r10, 95
+; P8BE-NEXT: sub r3, r5, r3
+; P8BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha
+; P8BE-NEXT: mtvsrwz v2, r3
+; P8BE-NEXT: addi r3, r5, .LCPI0_0@toc@l
+; P8BE-NEXT: sub r6, r6, r8
+; P8BE-NEXT: lxvw4x v3, 0, r3
+; P8BE-NEXT: sub r3, r7, r9
; P8BE-NEXT: sub r4, r4, r10
-; P8BE-NEXT: mtvsrwz v4, r8
+; P8BE-NEXT: mtvsrwz v4, r6
; P8BE-NEXT: mtvsrwz v5, r3
; P8BE-NEXT: mtvsrwz v0, r4
; P8BE-NEXT: vperm v2, v4, v2, v3
-; P8BE-NEXT: vperm v3, v5, v0, v3
+; P8BE-NEXT: vperm v3, v0, v5, v3
; P8BE-NEXT: xxmrghw v2, v3, v2
; P8BE-NEXT: blr
%1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
; P9LE-LABEL: fold_urem_vec_2:
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
-; P9LE-NEXT: lis r4, 22765
+; P9LE-NEXT: lis r4, 689
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: ori r4, r4, 8969
+; P9LE-NEXT: ori r4, r4, 55879
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4
-; P9LE-NEXT: sub r6, r3, r5
-; P9LE-NEXT: srwi r6, r6, 1
-; P9LE-NEXT: add r5, r6, r5
-; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4
-; P9LE-NEXT: sub r6, r3, r5
-; P9LE-NEXT: srwi r6, r6, 1
-; P9LE-NEXT: add r5, r6, r5
-; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4
-; P9LE-NEXT: sub r6, r3, r5
-; P9LE-NEXT: srwi r6, r6, 1
-; P9LE-NEXT: add r5, r6, r5
-; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r5, r5, 95
; P9LE-NEXT: sub r3, r3, r5
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: sub r5, r3, r4
-; P9LE-NEXT: srwi r5, r5, 1
-; P9LE-NEXT: add r4, r5, r4
-; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3
; P9BE-LABEL: fold_urem_vec_2:
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
-; P9BE-NEXT: lis r4, 22765
+; P9BE-NEXT: lis r4, 689
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: ori r4, r4, 8969
+; P9BE-NEXT: ori r4, r4, 55879
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r5, r3, r4
-; P9BE-NEXT: sub r6, r3, r5
-; P9BE-NEXT: srwi r6, r6, 1
-; P9BE-NEXT: add r5, r6, r5
-; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r5, r3, r4
-; P9BE-NEXT: sub r6, r3, r5
-; P9BE-NEXT: srwi r6, r6, 1
-; P9BE-NEXT: add r5, r6, r5
-; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: xxperm vs0, vs1, vs2
; P9BE-NEXT: mulhwu r5, r3, r4
-; P9BE-NEXT: sub r6, r3, r5
-; P9BE-NEXT: srwi r6, r6, 1
-; P9BE-NEXT: add r5, r6, r5
-; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r5, r5, 95
; P9BE-NEXT: sub r3, r3, r5
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: sub r5, r3, r4
-; P9BE-NEXT: srwi r5, r5, 1
-; P9BE-NEXT: add r4, r5, r4
-; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtfprwz f3, r3
; P8LE-LABEL: fold_urem_vec_2:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r3, 22765
-; P8LE-NEXT: ori r3, r3, 8969
+; P8LE-NEXT: lis r3, 689
+; P8LE-NEXT: ori r3, r3, 55879
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r6, r4, 48, 48
-; P8LE-NEXT: clrlwi r5, r5, 16
; P8LE-NEXT: rldicl r7, r4, 32, 48
+; P8LE-NEXT: rldicl r4, r4, 16, 48
+; P8LE-NEXT: clrlwi r5, r5, 16
; P8LE-NEXT: clrlwi r6, r6, 16
; P8LE-NEXT: mulhwu r8, r5, r3
-; P8LE-NEXT: rldicl r4, r4, 16, 48
; P8LE-NEXT: clrlwi r7, r7, 16
-; P8LE-NEXT: mulhwu r9, r6, r3
; P8LE-NEXT: clrlwi r4, r4, 16
+; P8LE-NEXT: mulhwu r9, r6, r3
; P8LE-NEXT: mulhwu r10, r7, r3
; P8LE-NEXT: mulhwu r3, r4, r3
-; P8LE-NEXT: sub r11, r5, r8
-; P8LE-NEXT: sub r12, r6, r9
-; P8LE-NEXT: srwi r11, r11, 1
-; P8LE-NEXT: add r8, r11, r8
-; P8LE-NEXT: sub r11, r7, r10
-; P8LE-NEXT: srwi r12, r12, 1
-; P8LE-NEXT: add r9, r12, r9
-; P8LE-NEXT: sub r12, r4, r3
-; P8LE-NEXT: srwi r11, r11, 1
-; P8LE-NEXT: srwi r8, r8, 6
-; P8LE-NEXT: add r10, r11, r10
-; P8LE-NEXT: srwi r11, r12, 1
-; P8LE-NEXT: srwi r9, r9, 6
-; P8LE-NEXT: add r3, r11, r3
; P8LE-NEXT: mulli r8, r8, 95
-; P8LE-NEXT: srwi r10, r10, 6
-; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: mulli r9, r9, 95
; P8LE-NEXT: mulli r10, r10, 95
; P8LE-NEXT: mulli r3, r3, 95
; P8BE-LABEL: fold_urem_vec_2:
; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2
-; P8BE-NEXT: lis r3, 22765
-; P8BE-NEXT: ori r3, r3, 8969
+; P8BE-NEXT: lis r3, 689
+; P8BE-NEXT: ori r3, r3, 55879
; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48
; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 32, 48
; P8BE-NEXT: clrlwi r6, r6, 16
-; P8BE-NEXT: mulhwu r8, r5, r3
; P8BE-NEXT: rldicl r4, r4, 16, 48
+; P8BE-NEXT: mulhwu r8, r5, r3
; P8BE-NEXT: clrlwi r7, r7, 16
-; P8BE-NEXT: mulhwu r9, r6, r3
; P8BE-NEXT: clrlwi r4, r4, 16
+; P8BE-NEXT: mulhwu r9, r6, r3
; P8BE-NEXT: mulhwu r10, r7, r3
; P8BE-NEXT: mulhwu r3, r4, r3
-; P8BE-NEXT: sub r11, r5, r8
-; P8BE-NEXT: sub r12, r6, r9
-; P8BE-NEXT: srwi r11, r11, 1
-; P8BE-NEXT: add r8, r11, r8
-; P8BE-NEXT: sub r11, r7, r10
-; P8BE-NEXT: srwi r12, r12, 1
-; P8BE-NEXT: add r9, r12, r9
-; P8BE-NEXT: sub r12, r4, r3
-; P8BE-NEXT: srwi r11, r11, 1
-; P8BE-NEXT: srwi r8, r8, 6
-; P8BE-NEXT: add r10, r11, r10
-; P8BE-NEXT: srwi r11, r12, 1
-; P8BE-NEXT: srwi r9, r9, 6
; P8BE-NEXT: mulli r8, r8, 95
-; P8BE-NEXT: add r3, r11, r3
-; P8BE-NEXT: srwi r10, r10, 6
-; P8BE-NEXT: srwi r3, r3, 6
; P8BE-NEXT: mulli r9, r9, 95
; P8BE-NEXT: mulli r10, r10, 95
; P8BE-NEXT: mulli r3, r3, 95
; P9LE-LABEL: combine_urem_udiv:
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
-; P9LE-NEXT: lis r4, 22765
+; P9LE-NEXT: lis r4, 689
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: ori r4, r4, 8969
+; P9LE-NEXT: ori r4, r4, 55879
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r5, r3, r4
-; P9LE-NEXT: sub r6, r3, r5
-; P9LE-NEXT: srwi r6, r6, 1
-; P9LE-NEXT: add r5, r6, r5
-; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r6, r5, 95
; P9LE-NEXT: sub r3, r3, r6
; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r6, r3, 16
-; P9LE-NEXT: mulhwu r7, r6, r4
-; P9LE-NEXT: sub r6, r6, r7
-; P9LE-NEXT: srwi r6, r6, 1
-; P9LE-NEXT: add r6, r6, r7
-; P9LE-NEXT: srwi r6, r6, 6
+; P9LE-NEXT: mulhwu r6, r6, r4
; P9LE-NEXT: mulli r7, r6, 95
; P9LE-NEXT: sub r3, r3, r7
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r7, r3, 16
-; P9LE-NEXT: mulhwu r8, r7, r4
-; P9LE-NEXT: sub r7, r7, r8
-; P9LE-NEXT: srwi r7, r7, 1
-; P9LE-NEXT: add r7, r7, r8
-; P9LE-NEXT: srwi r7, r7, 6
+; P9LE-NEXT: mulhwu r7, r7, r4
; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: sub r3, r3, r8
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r8, r3, 16
; P9LE-NEXT: mulhwu r4, r8, r4
-; P9LE-NEXT: sub r8, r8, r4
-; P9LE-NEXT: srwi r8, r8, 1
-; P9LE-NEXT: add r4, r8, r4
-; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r8, r4, 95
; P9LE-NEXT: mtvsrd v5, r4
; P9LE-NEXT: sub r3, r3, r8
; P9BE-LABEL: combine_urem_udiv:
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
-; P9BE-NEXT: lis r5, 22765
+; P9BE-NEXT: lis r5, 689
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: ori r5, r5, 8969
+; P9BE-NEXT: ori r5, r5, 55879
; P9BE-NEXT: clrlwi r4, r3, 16
-; P9BE-NEXT: mulhwu r6, r4, r5
-; P9BE-NEXT: sub r4, r4, r6
-; P9BE-NEXT: srwi r4, r4, 1
-; P9BE-NEXT: add r4, r4, r6
-; P9BE-NEXT: srwi r4, r4, 6
+; P9BE-NEXT: mulhwu r4, r4, r5
; P9BE-NEXT: mulli r6, r4, 95
; P9BE-NEXT: sub r3, r3, r6
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r6, r3, 16
-; P9BE-NEXT: mulhwu r7, r6, r5
-; P9BE-NEXT: sub r6, r6, r7
-; P9BE-NEXT: srwi r6, r6, 1
-; P9BE-NEXT: add r6, r6, r7
-; P9BE-NEXT: srwi r6, r6, 6
+; P9BE-NEXT: mulhwu r6, r6, r5
; P9BE-NEXT: mulli r7, r6, 95
; P9BE-NEXT: sub r3, r3, r7
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r7, r3, 16
; P9BE-NEXT: xxperm vs0, vs1, vs2
-; P9BE-NEXT: mulhwu r8, r7, r5
-; P9BE-NEXT: sub r7, r7, r8
-; P9BE-NEXT: srwi r7, r7, 1
-; P9BE-NEXT: add r7, r7, r8
-; P9BE-NEXT: srwi r7, r7, 6
+; P9BE-NEXT: mulhwu r7, r7, r5
; P9BE-NEXT: mulli r8, r7, 95
; P9BE-NEXT: sub r3, r3, r8
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r5, r3, r5
-; P9BE-NEXT: sub r8, r3, r5
-; P9BE-NEXT: srwi r8, r8, 1
-; P9BE-NEXT: add r5, r8, r5
-; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r8, r5, 95
; P9BE-NEXT: sub r3, r3, r8
; P9BE-NEXT: mtfprwz f3, r3
; P8LE-LABEL: combine_urem_udiv:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r3, 22765
-; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
-; P8LE-NEXT: ori r3, r3, 8969
+; P8LE-NEXT: lis r3, 689
+; P8LE-NEXT: ori r3, r3, 55879
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r6, r4, 48, 48
; P8LE-NEXT: rldicl r7, r4, 32, 48
; P8LE-NEXT: rldicl r4, r4, 16, 48
; P8LE-NEXT: mulhwu r9, r5, r3
-; P8LE-NEXT: mulhwu r11, r8, r3
+; P8LE-NEXT: mulhwu r8, r8, r3
; P8LE-NEXT: clrlwi r10, r7, 16
-; P8LE-NEXT: clrlwi r12, r4, 16
-; P8LE-NEXT: mulhwu r0, r10, r3
-; P8LE-NEXT: mulhwu r3, r12, r3
-; P8LE-NEXT: sub r30, r5, r9
-; P8LE-NEXT: sub r8, r8, r11
-; P8LE-NEXT: srwi r30, r30, 1
-; P8LE-NEXT: srwi r8, r8, 1
-; P8LE-NEXT: sub r10, r10, r0
-; P8LE-NEXT: add r9, r30, r9
-; P8LE-NEXT: add r8, r8, r11
-; P8LE-NEXT: sub r11, r12, r3
-; P8LE-NEXT: srwi r10, r10, 1
-; P8LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
-; P8LE-NEXT: srwi r9, r9, 6
-; P8LE-NEXT: srwi r11, r11, 1
-; P8LE-NEXT: srwi r8, r8, 6
-; P8LE-NEXT: add r10, r10, r0
-; P8LE-NEXT: mulli r12, r9, 95
-; P8LE-NEXT: add r3, r11, r3
+; P8LE-NEXT: clrlwi r11, r4, 16
+; P8LE-NEXT: mulhwu r10, r10, r3
+; P8LE-NEXT: mulhwu r3, r11, r3
+; P8LE-NEXT: mulli r11, r9, 95
; P8LE-NEXT: mtvsrd v2, r9
-; P8LE-NEXT: srwi r10, r10, 6
; P8LE-NEXT: mulli r9, r8, 95
-; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: mtvsrd v3, r8
; P8LE-NEXT: mulli r8, r10, 95
; P8LE-NEXT: mtvsrd v4, r10
; P8LE-NEXT: mulli r10, r3, 95
; P8LE-NEXT: vmrghh v2, v3, v2
-; P8LE-NEXT: sub r5, r5, r12
+; P8LE-NEXT: sub r5, r5, r11
; P8LE-NEXT: sub r6, r6, r9
; P8LE-NEXT: mtvsrd v3, r5
-; P8LE-NEXT: mtvsrd v5, r6
; P8LE-NEXT: sub r5, r7, r8
+; P8LE-NEXT: mtvsrd v5, r6
; P8LE-NEXT: sub r4, r4, r10
; P8LE-NEXT: mtvsrd v0, r5
; P8LE-NEXT: mtvsrd v1, r4
;
; P8BE-LABEL: combine_urem_udiv:
; P8BE: # %bb.0:
-; P8BE-NEXT: mfvsrd r5, v2
-; P8BE-NEXT: lis r4, 22765
-; P8BE-NEXT: ori r4, r4, 8969
-; P8BE-NEXT: clrldi r3, r5, 48
-; P8BE-NEXT: rldicl r6, r5, 48, 48
-; P8BE-NEXT: clrlwi r8, r3, 16
+; P8BE-NEXT: mfvsrd r4, v2
+; P8BE-NEXT: lis r3, 689
+; P8BE-NEXT: addis r11, r2, .LCPI2_0@toc@ha
+; P8BE-NEXT: ori r3, r3, 55879
+; P8BE-NEXT: addi r11, r11, .LCPI2_0@toc@l
+; P8BE-NEXT: clrldi r5, r4, 48
+; P8BE-NEXT: rldicl r6, r4, 48, 48
+; P8BE-NEXT: lxvw4x v2, 0, r11
+; P8BE-NEXT: clrlwi r8, r5, 16
; P8BE-NEXT: clrlwi r9, r6, 16
-; P8BE-NEXT: rldicl r7, r5, 32, 48
-; P8BE-NEXT: rldicl r5, r5, 16, 48
-; P8BE-NEXT: mulhwu r10, r8, r4
-; P8BE-NEXT: mulhwu r12, r9, r4
-; P8BE-NEXT: clrlwi r11, r7, 16
-; P8BE-NEXT: clrlwi r5, r5, 16
-; P8BE-NEXT: mulhwu r0, r11, r4
-; P8BE-NEXT: mulhwu r4, r5, r4
-; P8BE-NEXT: sub r8, r8, r10
-; P8BE-NEXT: sub r9, r9, r12
-; P8BE-NEXT: srwi r8, r8, 1
-; P8BE-NEXT: srwi r9, r9, 1
-; P8BE-NEXT: sub r11, r11, r0
-; P8BE-NEXT: add r8, r8, r10
-; P8BE-NEXT: add r9, r9, r12
-; P8BE-NEXT: sub r12, r5, r4
-; P8BE-NEXT: addis r10, r2, .LCPI2_0@toc@ha
-; P8BE-NEXT: srwi r11, r11, 1
-; P8BE-NEXT: srwi r8, r8, 6
-; P8BE-NEXT: srwi r12, r12, 1
-; P8BE-NEXT: srwi r9, r9, 6
-; P8BE-NEXT: addi r10, r10, .LCPI2_0@toc@l
-; P8BE-NEXT: add r11, r11, r0
-; P8BE-NEXT: mulli r0, r8, 95
-; P8BE-NEXT: add r4, r12, r4
+; P8BE-NEXT: rldicl r7, r4, 32, 48
+; P8BE-NEXT: rldicl r4, r4, 16, 48
+; P8BE-NEXT: mulhwu r8, r8, r3
+; P8BE-NEXT: mulhwu r9, r9, r3
+; P8BE-NEXT: clrlwi r10, r7, 16
+; P8BE-NEXT: clrlwi r4, r4, 16
+; P8BE-NEXT: mulhwu r10, r10, r3
+; P8BE-NEXT: mulhwu r3, r4, r3
+; P8BE-NEXT: mulli r12, r8, 95
; P8BE-NEXT: mtvsrwz v3, r8
-; P8BE-NEXT: lxvw4x v2, 0, r10
-; P8BE-NEXT: srwi r10, r11, 6
; P8BE-NEXT: mulli r8, r9, 95
-; P8BE-NEXT: srwi r4, r4, 6
; P8BE-NEXT: mtvsrwz v4, r9
; P8BE-NEXT: mulli r9, r10, 95
; P8BE-NEXT: mtvsrwz v5, r10
-; P8BE-NEXT: mulli r10, r4, 95
+; P8BE-NEXT: mulli r10, r3, 95
; P8BE-NEXT: vperm v3, v4, v3, v2
-; P8BE-NEXT: sub r3, r3, r0
+; P8BE-NEXT: sub r5, r5, r12
; P8BE-NEXT: sub r6, r6, r8
-; P8BE-NEXT: mtvsrwz v4, r3
+; P8BE-NEXT: mtvsrwz v4, r5
+; P8BE-NEXT: sub r5, r7, r9
; P8BE-NEXT: mtvsrwz v0, r6
-; P8BE-NEXT: sub r3, r7, r9
-; P8BE-NEXT: sub r5, r5, r10
-; P8BE-NEXT: mtvsrwz v1, r3
-; P8BE-NEXT: mtvsrwz v6, r5
+; P8BE-NEXT: sub r4, r4, r10
+; P8BE-NEXT: mtvsrwz v1, r5
+; P8BE-NEXT: mtvsrwz v6, r4
; P8BE-NEXT: vperm v4, v0, v4, v2
-; P8BE-NEXT: mtvsrwz v0, r4
+; P8BE-NEXT: mtvsrwz v0, r3
; P8BE-NEXT: vperm v1, v6, v1, v2
; P8BE-NEXT: vperm v2, v0, v5, v2
; P8BE-NEXT: xxmrghw v4, v1, v4
; P9LE-LABEL: dont_fold_urem_power_of_two:
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0
-; P9LE-NEXT: lis r4, 22765
+; P9LE-NEXT: lis r4, 689
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: ori r4, r4, 8969
+; P9LE-NEXT: ori r4, r4, 55879
; P9LE-NEXT: clrlwi r3, r3, 26
; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: sub r5, r3, r4
-; P9LE-NEXT: srwi r5, r5, 1
-; P9LE-NEXT: add r4, r5, r4
-; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v4, r3
; P9BE-LABEL: dont_fold_urem_power_of_two:
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2
-; P9BE-NEXT: lis r4, 22765
+; P9BE-NEXT: lis r4, 689
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: ori r4, r4, 8969
+; P9BE-NEXT: ori r4, r4, 55879
; P9BE-NEXT: clrlwi r3, r3, 27
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: xxperm vs0, vs1, vs2
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: sub r5, r3, r4
-; P9BE-NEXT: srwi r5, r5, 1
-; P9BE-NEXT: add r4, r5, r4
-; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtfprwz f1, r3
; P8LE-LABEL: dont_fold_urem_power_of_two:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r3, 22765
-; P8LE-NEXT: ori r3, r3, 8969
+; P8LE-NEXT: lis r3, 689
+; P8LE-NEXT: ori r3, r3, 55879
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48
-; P8LE-NEXT: rldicl r7, r4, 48, 48
-; P8LE-NEXT: clrlwi r5, r5, 16
-; P8LE-NEXT: mulhwu r3, r5, r3
-; P8LE-NEXT: sub r6, r5, r3
-; P8LE-NEXT: srwi r6, r6, 1
-; P8LE-NEXT: add r3, r6, r3
; P8LE-NEXT: clrldi r6, r4, 48
-; P8LE-NEXT: srwi r3, r3, 6
+; P8LE-NEXT: clrlwi r5, r5, 16
; P8LE-NEXT: clrlwi r6, r6, 26
-; P8LE-NEXT: mulli r3, r3, 95
-; P8LE-NEXT: rldicl r4, r4, 32, 48
+; P8LE-NEXT: mulhwu r3, r5, r3
+; P8LE-NEXT: rldicl r7, r4, 48, 48
; P8LE-NEXT: mtvsrd v2, r6
+; P8LE-NEXT: rldicl r4, r4, 32, 48
; P8LE-NEXT: clrlwi r6, r7, 27
; P8LE-NEXT: clrlwi r4, r4, 29
; P8LE-NEXT: mtvsrd v3, r6
-; P8LE-NEXT: mtvsrd v5, r4
+; P8LE-NEXT: mtvsrd v4, r4
+; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: vmrghh v2, v3, v2
; P8LE-NEXT: sub r3, r5, r3
-; P8LE-NEXT: mtvsrd v4, r3
-; P8LE-NEXT: vmrghh v3, v4, v5
+; P8LE-NEXT: mtvsrd v5, r3
+; P8LE-NEXT: vmrghh v3, v5, v4
; P8LE-NEXT: xxmrglw v2, v3, v2
; P8LE-NEXT: blr
;
; P8BE-LABEL: dont_fold_urem_power_of_two:
; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2
-; P8BE-NEXT: lis r3, 22765
+; P8BE-NEXT: lis r3, 689
; P8BE-NEXT: addis r7, r2, .LCPI3_0@toc@ha
-; P8BE-NEXT: ori r3, r3, 8969
+; P8BE-NEXT: ori r3, r3, 55879
; P8BE-NEXT: clrldi r5, r4, 48
-; P8BE-NEXT: rldicl r8, r4, 16, 48
-; P8BE-NEXT: clrlwi r5, r5, 16
-; P8BE-NEXT: mulhwu r3, r5, r3
-; P8BE-NEXT: sub r6, r5, r3
-; P8BE-NEXT: srwi r6, r6, 1
-; P8BE-NEXT: add r3, r6, r3
; P8BE-NEXT: rldicl r6, r4, 32, 48
-; P8BE-NEXT: srwi r3, r3, 6
+; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: clrlwi r6, r6, 27
-; P8BE-NEXT: mulli r3, r3, 95
+; P8BE-NEXT: mulhwu r3, r5, r3
+; P8BE-NEXT: rldicl r8, r4, 16, 48
; P8BE-NEXT: mtvsrwz v2, r6
; P8BE-NEXT: addi r6, r7, .LCPI3_0@toc@l
; P8BE-NEXT: rldicl r4, r4, 48, 48
; P8BE-NEXT: clrlwi r4, r4, 29
; P8BE-NEXT: mtvsrwz v4, r7
; P8BE-NEXT: mtvsrwz v0, r4
-; P8BE-NEXT: sub r3, r5, r3
+; P8BE-NEXT: mulli r3, r3, 95
; P8BE-NEXT: vperm v2, v4, v2, v3
+; P8BE-NEXT: sub r3, r5, r3
; P8BE-NEXT: mtvsrwz v5, r3
; P8BE-NEXT: vperm v3, v0, v5, v3
; P8BE-NEXT: xxmrghw v2, v2, v3
; P9LE-LABEL: dont_fold_urem_one:
; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 4
-; P9LE-NEXT: lis r4, -19946
-; P9LE-NEXT: lis r5, -14230
+; P9LE-NEXT: lis r4, 2849
; P9LE-NEXT: vextuhrx r3, r3, v2
-; P9LE-NEXT: ori r4, r4, 17097
-; P9LE-NEXT: ori r5, r5, 30865
+; P9LE-NEXT: ori r4, r4, 25645
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: srwi r4, r4, 4
; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: sub r3, r3, r4
-; P9LE-NEXT: lis r4, 24749
+; P9LE-NEXT: lis r4, 12
; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 6
-; P9LE-NEXT: ori r4, r4, 47143
+; P9LE-NEXT: ori r4, r4, 5560
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mulhwu r4, r3, r4
-; P9LE-NEXT: srwi r4, r4, 11
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4
+; P9LE-NEXT: lis r4, 100
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 2
+; P9LE-NEXT: ori r4, r4, 13629
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
-; P9LE-NEXT: clrlwi r4, r3, 16
-; P9LE-NEXT: rlwinm r3, r3, 31, 17, 31
-; P9LE-NEXT: mulhwu r3, r3, r5
-; P9LE-NEXT: srwi r3, r3, 8
-; P9LE-NEXT: mulli r3, r3, 654
-; P9LE-NEXT: sub r3, r4, r3
+; P9LE-NEXT: clrlwi r3, r3, 16
+; P9LE-NEXT: mulhwu r4, r3, r4
+; P9LE-NEXT: mulli r4, r4, 654
+; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3
; P9LE-NEXT: li r3, 0
; P9LE-NEXT: mtvsrd v4, r3
; P9BE-LABEL: dont_fold_urem_one:
; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6
-; P9BE-NEXT: lis r4, 24749
-; P9BE-NEXT: lis r5, -14230
+; P9BE-NEXT: lis r4, 12
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: ori r4, r4, 47143
-; P9BE-NEXT: ori r5, r5, 30865
+; P9BE-NEXT: ori r4, r4, 5560
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: srwi r4, r4, 11
; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sub r3, r3, r4
-; P9BE-NEXT: lis r4, -19946
+; P9BE-NEXT: lis r4, 2849
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 4
-; P9BE-NEXT: ori r4, r4, 17097
+; P9BE-NEXT: ori r4, r4, 25645
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mulhwu r4, r3, r4
-; P9BE-NEXT: srwi r4, r4, 4
; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: sub r3, r3, r4
+; P9BE-NEXT: lis r4, 100
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
+; P9BE-NEXT: ori r4, r4, 13629
; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
; P9BE-NEXT: lxv vs2, 0(r3)
; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2
-; P9BE-NEXT: clrlwi r4, r3, 16
-; P9BE-NEXT: rlwinm r3, r3, 31, 17, 31
+; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: xxperm vs0, vs1, vs2
-; P9BE-NEXT: mulhwu r3, r3, r5
-; P9BE-NEXT: srwi r3, r3, 8
-; P9BE-NEXT: mulli r3, r3, 654
-; P9BE-NEXT: sub r3, r4, r3
+; P9BE-NEXT: mulhwu r4, r3, r4
+; P9BE-NEXT: mulli r4, r4, 654
+; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: li r3, 0
; P9BE-NEXT: mtfprwz f3, r3
; P8LE-LABEL: dont_fold_urem_one:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r3, -14230
-; P8LE-NEXT: lis r7, -19946
-; P8LE-NEXT: lis r9, 24749
-; P8LE-NEXT: ori r3, r3, 30865
-; P8LE-NEXT: ori r7, r7, 17097
+; P8LE-NEXT: lis r3, 100
+; P8LE-NEXT: lis r7, 2849
+; P8LE-NEXT: lis r8, 12
+; P8LE-NEXT: li r9, 0
+; P8LE-NEXT: ori r3, r3, 13629
+; P8LE-NEXT: ori r7, r7, 25645
+; P8LE-NEXT: ori r8, r8, 5560
+; P8LE-NEXT: mtvsrd v2, r9
; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 48, 48
; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r4, r4, 16, 48
-; P8LE-NEXT: rlwinm r8, r5, 31, 17, 31
-; P8LE-NEXT: clrlwi r6, r6, 16
; P8LE-NEXT: clrlwi r5, r5, 16
-; P8LE-NEXT: mulhwu r3, r8, r3
-; P8LE-NEXT: ori r8, r9, 47143
+; P8LE-NEXT: clrlwi r6, r6, 16
+; P8LE-NEXT: mulhwu r3, r5, r3
; P8LE-NEXT: clrlwi r4, r4, 16
-; P8LE-NEXT: li r9, 0
; P8LE-NEXT: mulhwu r7, r6, r7
; P8LE-NEXT: mulhwu r8, r4, r8
-; P8LE-NEXT: mtvsrd v2, r9
-; P8LE-NEXT: srwi r3, r3, 8
-; P8LE-NEXT: srwi r7, r7, 4
; P8LE-NEXT: mulli r3, r3, 654
-; P8LE-NEXT: srwi r8, r8, 11
; P8LE-NEXT: mulli r7, r7, 23
; P8LE-NEXT: mulli r8, r8, 5423
; P8LE-NEXT: sub r3, r5, r3
; P8BE-LABEL: dont_fold_urem_one:
; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2
-; P8BE-NEXT: lis r3, 24749
-; P8BE-NEXT: lis r7, -19946
-; P8BE-NEXT: lis r8, -14230
+; P8BE-NEXT: lis r3, 12
+; P8BE-NEXT: lis r7, 2849
+; P8BE-NEXT: lis r8, 100
+; P8BE-NEXT: addis r9, r2, .LCPI4_0@toc@ha
; P8BE-NEXT: li r10, 0
-; P8BE-NEXT: ori r3, r3, 47143
-; P8BE-NEXT: ori r7, r7, 17097
-; P8BE-NEXT: ori r8, r8, 30865
+; P8BE-NEXT: ori r3, r3, 5560
+; P8BE-NEXT: ori r7, r7, 25645
+; P8BE-NEXT: ori r8, r8, 13629
; P8BE-NEXT: mtvsrwz v2, r10
; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48
-; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r4, r4, 32, 48
+; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: mulhwu r3, r5, r3
-; P8BE-NEXT: rlwinm r9, r4, 31, 17, 31
+; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulhwu r7, r6, r7
-; P8BE-NEXT: mulhwu r8, r9, r8
-; P8BE-NEXT: addis r9, r2, .LCPI4_0@toc@ha
-; P8BE-NEXT: srwi r3, r3, 11
+; P8BE-NEXT: mulhwu r8, r4, r8
; P8BE-NEXT: mulli r3, r3, 5423
-; P8BE-NEXT: srwi r7, r7, 4
-; P8BE-NEXT: srwi r8, r8, 8
; P8BE-NEXT: mulli r7, r7, 23
; P8BE-NEXT: mulli r8, r8, 654
; P8BE-NEXT: sub r3, r5, r3
; P8BE-NEXT: addi r5, r9, .LCPI4_0@toc@l
-; P8BE-NEXT: mtvsrwz v4, r3
-; P8BE-NEXT: clrlwi r3, r4, 16
; P8BE-NEXT: lxvw4x v3, 0, r5
; P8BE-NEXT: sub r5, r6, r7
-; P8BE-NEXT: sub r3, r3, r8
+; P8BE-NEXT: mtvsrwz v4, r3
+; P8BE-NEXT: sub r3, r4, r8
; P8BE-NEXT: mtvsrwz v5, r5
; P8BE-NEXT: mtvsrwz v0, r3
; P8BE-NEXT: vperm v4, v5, v4, v3
; RV32IM-NEXT: lhu a3, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1)
; RV32IM-NEXT: lhu a1, 4(a1)
-; RV32IM-NEXT: lui a5, 364242
-; RV32IM-NEXT: addi a5, a5, 777
+; RV32IM-NEXT: lui a5, 11038
+; RV32IM-NEXT: addi a5, a5, -1465
; RV32IM-NEXT: mulhu a5, a4, a5
-; RV32IM-NEXT: sub a6, a4, a5
-; RV32IM-NEXT: srli a6, a6, 1
-; RV32IM-NEXT: add a5, a6, a5
-; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: li a6, 95
; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a4, a4, a5
-; RV32IM-NEXT: srli a5, a1, 2
-; RV32IM-NEXT: lui a6, 135300
-; RV32IM-NEXT: addi a6, a6, 529
-; RV32IM-NEXT: mulhu a5, a5, a6
-; RV32IM-NEXT: srli a5, a5, 2
+; RV32IM-NEXT: lui a5, 8456
+; RV32IM-NEXT: addi a5, a5, 1058
+; RV32IM-NEXT: mulhu a5, a1, a5
; RV32IM-NEXT: li a6, 124
; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a1, a1, a5
-; RV32IM-NEXT: lui a5, 342392
-; RV32IM-NEXT: addi a5, a5, 669
+; RV32IM-NEXT: lui a5, 10700
+; RV32IM-NEXT: addi a5, a5, -1003
; RV32IM-NEXT: mulhu a5, a3, a5
-; RV32IM-NEXT: srli a5, a5, 5
; RV32IM-NEXT: li a6, 98
; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a3, a3, a5
-; RV32IM-NEXT: lui a5, 267633
-; RV32IM-NEXT: addi a5, a5, -1809
+; RV32IM-NEXT: lui a5, 1045
+; RV32IM-NEXT: addi a5, a5, 1801
; RV32IM-NEXT: mulhu a5, a2, a5
-; RV32IM-NEXT: srli a5, a5, 8
; RV32IM-NEXT: li a6, 1003
; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a2, a2, a5
; RV64IM-NEXT: lhu a5, 16(a1)
; RV64IM-NEXT: lhu a1, 8(a1)
; RV64IM-NEXT: mulhu a3, a2, a3
-; RV64IM-NEXT: sub a6, a2, a3
-; RV64IM-NEXT: srli a6, a6, 1
-; RV64IM-NEXT: add a3, a6, a3
-; RV64IM-NEXT: srli a3, a3, 6
-; RV64IM-NEXT: li a6, 95
-; RV64IM-NEXT: lui a7, %hi(.LCPI0_1)
-; RV64IM-NEXT: ld a7, %lo(.LCPI0_1)(a7)
-; RV64IM-NEXT: mulw a3, a3, a6
+; RV64IM-NEXT: lui a6, %hi(.LCPI0_1)
+; RV64IM-NEXT: ld a6, %lo(.LCPI0_1)(a6)
+; RV64IM-NEXT: li a7, 95
+; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a2, a2, a3
-; RV64IM-NEXT: srli a3, a1, 2
-; RV64IM-NEXT: mulhu a3, a3, a7
-; RV64IM-NEXT: srli a3, a3, 3
-; RV64IM-NEXT: li a6, 124
-; RV64IM-NEXT: lui a7, %hi(.LCPI0_2)
-; RV64IM-NEXT: ld a7, %lo(.LCPI0_2)(a7)
-; RV64IM-NEXT: mulw a3, a3, a6
+; RV64IM-NEXT: mulhu a3, a1, a6
+; RV64IM-NEXT: lui a6, %hi(.LCPI0_2)
+; RV64IM-NEXT: ld a6, %lo(.LCPI0_2)(a6)
+; RV64IM-NEXT: li a7, 124
+; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a1, a1, a3
-; RV64IM-NEXT: srli a3, a5, 1
-; RV64IM-NEXT: mulhu a3, a3, a7
-; RV64IM-NEXT: srli a3, a3, 4
+; RV64IM-NEXT: mulhu a3, a5, a6
; RV64IM-NEXT: lui a6, %hi(.LCPI0_3)
; RV64IM-NEXT: ld a6, %lo(.LCPI0_3)(a6)
; RV64IM-NEXT: li a7, 98
; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a5, a5, a3
; RV64IM-NEXT: mulhu a3, a4, a6
-; RV64IM-NEXT: srli a3, a3, 7
; RV64IM-NEXT: li a6, 1003
; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a4, a4, a3
; RV32IM-NEXT: lhu a3, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1)
; RV32IM-NEXT: lhu a1, 4(a1)
-; RV32IM-NEXT: lui a5, 364242
-; RV32IM-NEXT: addi a5, a5, 777
+; RV32IM-NEXT: lui a5, 11038
+; RV32IM-NEXT: addi a5, a5, -1465
; RV32IM-NEXT: mulhu a6, a4, a5
-; RV32IM-NEXT: sub a7, a4, a6
-; RV32IM-NEXT: srli a7, a7, 1
-; RV32IM-NEXT: add a6, a7, a6
-; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: li a7, 95
; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a4, a4, a6
; RV32IM-NEXT: mulhu a6, a1, a5
-; RV32IM-NEXT: sub t0, a1, a6
-; RV32IM-NEXT: srli t0, t0, 1
-; RV32IM-NEXT: add a6, t0, a6
-; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a1, a1, a6
; RV32IM-NEXT: mulhu a6, a3, a5
-; RV32IM-NEXT: sub t0, a3, a6
-; RV32IM-NEXT: srli t0, t0, 1
-; RV32IM-NEXT: add a6, t0, a6
-; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a3, a3, a6
; RV32IM-NEXT: mulhu a5, a2, a5
-; RV32IM-NEXT: sub a6, a2, a5
-; RV32IM-NEXT: srli a6, a6, 1
-; RV32IM-NEXT: add a5, a6, a5
-; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: mul a5, a5, a7
; RV32IM-NEXT: sub a2, a2, a5
; RV32IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: lhu a5, 16(a1)
; RV64IM-NEXT: lhu a1, 8(a1)
; RV64IM-NEXT: mulhu a6, a2, a3
-; RV64IM-NEXT: sub a7, a2, a6
-; RV64IM-NEXT: srli a7, a7, 1
-; RV64IM-NEXT: add a6, a7, a6
-; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a2, a2, a6
; RV64IM-NEXT: mulhu a6, a1, a3
-; RV64IM-NEXT: sub t0, a1, a6
-; RV64IM-NEXT: srli t0, t0, 1
-; RV64IM-NEXT: add a6, t0, a6
-; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a1, a1, a6
; RV64IM-NEXT: mulhu a6, a5, a3
-; RV64IM-NEXT: sub t0, a5, a6
-; RV64IM-NEXT: srli t0, t0, 1
-; RV64IM-NEXT: add a6, t0, a6
-; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a5, a5, a6
; RV64IM-NEXT: mulhu a3, a4, a3
-; RV64IM-NEXT: sub a6, a4, a3
-; RV64IM-NEXT: srli a6, a6, 1
-; RV64IM-NEXT: add a3, a6, a3
-; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a4, a4, a3
; RV64IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1)
; RV32IM-NEXT: lhu a1, 8(a1)
-; RV32IM-NEXT: lui a5, 364242
-; RV32IM-NEXT: addi a5, a5, 777
+; RV32IM-NEXT: lui a5, 11038
+; RV32IM-NEXT: addi a5, a5, -1465
; RV32IM-NEXT: mulhu a6, a4, a5
-; RV32IM-NEXT: sub a7, a4, a6
-; RV32IM-NEXT: srli a7, a7, 1
-; RV32IM-NEXT: add a6, a7, a6
-; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: li a7, 95
; RV32IM-NEXT: mul t0, a6, a7
; RV32IM-NEXT: mulhu t1, a1, a5
-; RV32IM-NEXT: sub t2, a1, t1
-; RV32IM-NEXT: srli t2, t2, 1
-; RV32IM-NEXT: add t1, t2, t1
-; RV32IM-NEXT: srli t1, t1, 6
; RV32IM-NEXT: mul t2, t1, a7
; RV32IM-NEXT: mulhu t3, a3, a5
-; RV32IM-NEXT: sub t4, a3, t3
-; RV32IM-NEXT: srli t4, t4, 1
-; RV32IM-NEXT: add t3, t4, t3
-; RV32IM-NEXT: srli t3, t3, 6
; RV32IM-NEXT: mul t4, t3, a7
; RV32IM-NEXT: mulhu a5, a2, a5
-; RV32IM-NEXT: sub t5, a2, a5
-; RV32IM-NEXT: srli t5, t5, 1
-; RV32IM-NEXT: add a5, t5, a5
-; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: mul a7, a5, a7
; RV32IM-NEXT: sub a5, a7, a5
; RV32IM-NEXT: sub a2, a2, a5
; RV64IM-NEXT: lhu a5, 8(a1)
; RV64IM-NEXT: lhu a1, 16(a1)
; RV64IM-NEXT: mulhu a6, a2, a3
-; RV64IM-NEXT: sub a7, a2, a6
-; RV64IM-NEXT: srli a7, a7, 1
-; RV64IM-NEXT: add a6, a7, a6
-; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw t0, a6, a7
; RV64IM-NEXT: mulhu t1, a1, a3
-; RV64IM-NEXT: sub t2, a1, t1
-; RV64IM-NEXT: srli t2, t2, 1
-; RV64IM-NEXT: add t1, t2, t1
-; RV64IM-NEXT: srli t1, t1, 6
; RV64IM-NEXT: mulw t2, t1, a7
; RV64IM-NEXT: mulhu t3, a5, a3
-; RV64IM-NEXT: sub t4, a5, t3
-; RV64IM-NEXT: srli t4, t4, 1
-; RV64IM-NEXT: add t3, t4, t3
-; RV64IM-NEXT: srli t3, t3, 6
; RV64IM-NEXT: mulw t4, t3, a7
; RV64IM-NEXT: mulhu a3, a4, a3
-; RV64IM-NEXT: sub t5, a4, a3
-; RV64IM-NEXT: srli t5, t5, 1
-; RV64IM-NEXT: add a3, t5, a3
-; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: mulw a7, a3, a7
; RV64IM-NEXT: subw a3, a7, a3
; RV64IM-NEXT: subw a4, a4, a3
; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1)
; RV32IM-NEXT: lhu a1, 0(a1)
-; RV32IM-NEXT: lui a5, 364242
-; RV32IM-NEXT: addi a5, a5, 777
+; RV32IM-NEXT: lui a5, 11038
+; RV32IM-NEXT: addi a5, a5, -1465
; RV32IM-NEXT: mulhu a5, a4, a5
-; RV32IM-NEXT: sub a6, a4, a5
-; RV32IM-NEXT: srli a6, a6, 1
-; RV32IM-NEXT: add a5, a6, a5
-; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: li a6, 95
; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a4, a4, a5
; RV64IM-NEXT: lhu a5, 8(a1)
; RV64IM-NEXT: lhu a1, 0(a1)
; RV64IM-NEXT: mulhu a3, a2, a3
-; RV64IM-NEXT: sub a6, a2, a3
-; RV64IM-NEXT: srli a6, a6, 1
-; RV64IM-NEXT: add a3, a6, a3
-; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: li a6, 95
; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a2, a2, a3
;
; RV32IM-LABEL: dont_fold_urem_one:
; RV32IM: # %bb.0:
-; RV32IM-NEXT: lhu a2, 4(a1)
-; RV32IM-NEXT: lhu a3, 12(a1)
+; RV32IM-NEXT: lhu a2, 12(a1)
+; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a1, 8(a1)
-; RV32IM-NEXT: srli a4, a2, 1
-; RV32IM-NEXT: lui a5, 820904
-; RV32IM-NEXT: addi a5, a5, -1903
-; RV32IM-NEXT: mulhu a4, a4, a5
-; RV32IM-NEXT: srli a4, a4, 8
+; RV32IM-NEXT: lui a4, 1603
+; RV32IM-NEXT: addi a4, a4, 1341
+; RV32IM-NEXT: mulhu a4, a3, a4
; RV32IM-NEXT: li a5, 654
; RV32IM-NEXT: mul a4, a4, a5
-; RV32IM-NEXT: sub a2, a2, a4
-; RV32IM-NEXT: lui a4, 729444
-; RV32IM-NEXT: addi a4, a4, 713
+; RV32IM-NEXT: sub a3, a3, a4
+; RV32IM-NEXT: lui a4, 45590
+; RV32IM-NEXT: addi a4, a4, 1069
; RV32IM-NEXT: mulhu a4, a1, a4
-; RV32IM-NEXT: srli a4, a4, 4
; RV32IM-NEXT: li a5, 23
; RV32IM-NEXT: mul a4, a4, a5
; RV32IM-NEXT: sub a1, a1, a4
-; RV32IM-NEXT: lui a4, 395996
-; RV32IM-NEXT: addi a4, a4, -2009
-; RV32IM-NEXT: mulhu a4, a3, a4
-; RV32IM-NEXT: srli a4, a4, 11
+; RV32IM-NEXT: lui a4, 193
+; RV32IM-NEXT: addi a4, a4, 1464
+; RV32IM-NEXT: mulhu a4, a2, a4
; RV32IM-NEXT: lui a5, 1
; RV32IM-NEXT: addi a5, a5, 1327
; RV32IM-NEXT: mul a4, a4, a5
-; RV32IM-NEXT: sub a3, a3, a4
+; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: sh zero, 0(a0)
-; RV32IM-NEXT: sh a3, 6(a0)
+; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a1, 4(a0)
-; RV32IM-NEXT: sh a2, 2(a0)
+; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: ret
;
; RV64I-LABEL: dont_fold_urem_one:
;
; RV64IM-LABEL: dont_fold_urem_one:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: lhu a2, 16(a1)
+; RV64IM-NEXT: lhu a2, 8(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI4_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI4_0)(a3)
; RV64IM-NEXT: lhu a4, 24(a1)
-; RV64IM-NEXT: lhu a1, 8(a1)
+; RV64IM-NEXT: lhu a1, 16(a1)
; RV64IM-NEXT: mulhu a3, a2, a3
-; RV64IM-NEXT: sub a5, a2, a3
-; RV64IM-NEXT: srli a5, a5, 1
-; RV64IM-NEXT: add a3, a5, a3
-; RV64IM-NEXT: srli a3, a3, 4
-; RV64IM-NEXT: li a5, 23
-; RV64IM-NEXT: lui a6, %hi(.LCPI4_1)
-; RV64IM-NEXT: ld a6, %lo(.LCPI4_1)(a6)
-; RV64IM-NEXT: mulw a3, a3, a5
+; RV64IM-NEXT: lui a5, %hi(.LCPI4_1)
+; RV64IM-NEXT: ld a5, %lo(.LCPI4_1)(a5)
+; RV64IM-NEXT: li a6, 654
+; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a2, a2, a3
-; RV64IM-NEXT: srli a3, a1, 1
-; RV64IM-NEXT: mulhu a3, a3, a6
-; RV64IM-NEXT: srli a3, a3, 7
+; RV64IM-NEXT: mulhu a3, a1, a5
; RV64IM-NEXT: lui a5, %hi(.LCPI4_2)
; RV64IM-NEXT: ld a5, %lo(.LCPI4_2)(a5)
-; RV64IM-NEXT: li a6, 654
+; RV64IM-NEXT: li a6, 23
; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a1, a1, a3
; RV64IM-NEXT: mulhu a3, a4, a5
-; RV64IM-NEXT: srli a3, a3, 12
; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mulw a3, a3, a5
; RV64IM-NEXT: subw a4, a4, a3
; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a4, 6(a0)
-; RV64IM-NEXT: sh a1, 2(a0)
-; RV64IM-NEXT: sh a2, 4(a0)
+; RV64IM-NEXT: sh a1, 4(a0)
+; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1