drm/amd/display: Support vertical interrupt 0 for all dcn ASIC
authorWayne Lin <Wayne.Lin@amd.com>
Wed, 10 Mar 2021 15:40:01 +0000 (23:40 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 20 Jul 2022 20:04:11 +0000 (16:04 -0400)
[Why]
When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try
to register vertical interrupt 0 for specific task.

Currently, only dcn10 have defined relevant info for vertical interrupt
0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will
get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and
cause pointer errors.

[How]
Add support of vertical interrupt 0 for all dcn ASIC.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

index 146cd18..2aa74ee 100644 (file)
@@ -289,6 +289,13 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
        }
 
+#define dmub_trace_int_entry()\
+       [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
+               IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
+                       DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
+               .funcs = &dmub_trace_irq_info_funcs\
+       }
+
 #define vline0_int_entry(reg_num)\
        [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
                IRQ_REG_ENTRY(OTG, reg_num,\
@@ -297,13 +304,6 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
                .funcs = &vline0_irq_info_funcs\
        }
 
-#define dmub_trace_int_entry()\
-       [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
-               IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
-                       DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
-               .funcs = &dmub_trace_irq_info_funcs\
-       }
-
 #define dummy_irq_entry() \
        {\
                .funcs = &dummy_irq_info_funcs\
index 66e6076..1d149d2 100644 (file)
@@ -24,6 +24,10 @@ static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_servi
                return DC_IRQ_SOURCE_VBLANK1;
        case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
                return DC_IRQ_SOURCE_VBLANK2;
+       case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC1_VLINE0;
+       case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC2_VLINE0;
        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
                return DC_IRQ_SOURCE_PFLIP1;
        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -96,6 +100,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .ack = NULL
 };
 
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -164,6 +173,14 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
        }
 
+#define vline0_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+               .funcs = &vline0_irq_info_funcs\
+       }
+
 #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
 
 #define i2c_int_entry(reg_num) \
@@ -236,6 +253,8 @@ static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBE
                vupdate_no_lock_int_entry(1),
                vblank_int_entry(0),
                vblank_int_entry(1),
+               vline0_int_entry(0),
+               vline0_int_entry(1),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn303 = {