//===----------------------------------------------------------------------===//
#include "X86CallLowering.h"
+#include "X86CallingConv.h"
#include "X86ISelLowering.h"
#include "X86InstrInfo.h"
#include "X86TargetMachine.h"
-#include "X86CallingConv.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
-#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
});
FuncReturnHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
- if(!handleAssignments(MIRBuilder, SplitArgs, Handler))
+ if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
return false;
}
int FI = MFI.CreateFixedObject(Size, Offset, true);
MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
- unsigned AddrReg =
- MRI.createGenericVirtualRegister(LLT::pointer(0,
- DL.getPointerSizeInBits(0)));
+ unsigned AddrReg = MRI.createGenericVirtualRegister(
+ LLT::pointer(0, DL.getPointerSizeInBits(0)));
MIRBuilder.buildFrameIndex(AddrReg, FI);
return AddrReg;
}
const DataLayout &DL;
};
-}
+} // namespace
bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
const Function &F,
if (F.arg_empty())
return true;
- //TODO: handle variadic function
+ // TODO: handle variadic function
if (F.isVarArg())
return false;
MachineBasicBlock &MBB = MIRBuilder.getMBB();
if (!MBB.empty())
- MIRBuilder.setInstr(*MBB.begin());
+ MIRBuilder.setInstr(*MBB.begin());
FormalArgHandler Handler(MIRBuilder, MRI, CC_X86, DL);
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
// No need to constrain SrcReg. It will get constrained when
// we hit another of its use or its defs.
// Copies do not have constraints.
- const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
+ const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
if (!OldRC || !RC->hasSubClassEq(OldRC)) {
if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
- DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
- << " operand\n");
- return false;
- }
+ DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+ << " operand\n");
+ return false;
+ }
}
I.setDesc(TII.get(X86::COPY));
return true;
assert(I.getNumOperands() == I.getNumExplicitOperands() &&
"Generic instruction has unexpected implicit operands\n");
- // TODO: This should be implemented by tblgen, pattern with predicate not supported yet.
+ // TODO: This should be implemented by tblgen, pattern with predicate not
+ // supported yet.
if (selectBinaryOp(I, MRI))
return true;
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
-
unsigned NumOperands = MI.getNumOperands();
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- if (NumOperands != 3 ||
- (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
+ if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
(Ty != MRI.getType(MI.getOperand(2).getReg())))
llvm_unreachable("Unsupported operand maping yet.");
ValMapIdx = VMI_3OpsFp64Idx;
break;
default:
- llvm_unreachable("Unsupported register size.");
+ llvm_unreachable("Unsupported register size.");
}
}
} else {