sys_poweroff = <0x84000008>;
};
- vpu {
- compatible = "amlogic, vpu-g12a";
+ vpu: vpu {
+ compatible = "amlogic, vpu-sm1";
dev_name = "vpu";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
sys_poweroff = <0x84000008>;
};
- vpu {
- compatible = "amlogic, vpu-g12a";
+ vpu: vpu {
+ compatible = "amlogic, vpu-sm1";
dev_name = "vpu";
status = "okay";
clocks = <&clkc CLKID_VAPB_MUX>,
/* v04: add g12a support */
/* v05: add txl support */
/* v20180925: add tl1 support */
-#define VPU_VERION "v20180925"
+/* v20190314: add sm1 support */
+#define VPU_VERION "v20190314"
int vpu_debug_print_flag;
static spinlock_t vpu_mem_lock;
static int vpu_resume(struct platform_device *pdev)
{
+ set_vpu_clk(vpu_conf.clk_level);
VPUPR("resume clk: %uHz(0x%x)\n",
get_vpu_clk(), (vpu_hiu_read(HHI_VPU_CLK_CNTL)));
- set_vpu_clk(vpu_conf.clk_level);
return 0;
}
#endif
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
.module_init_table_cnt =
sizeof(vpu_module_init_gxm) / sizeof(struct vpu_ctrl_s),
.module_init_table = vpu_module_init_gxm,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_gx,
};
.module_init_table_cnt =
sizeof(vpu_module_init_txlx) / sizeof(struct vpu_ctrl_s),
.module_init_table = vpu_module_init_txlx,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_txlx,
};
.module_init_table_cnt = 0,
.module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_gxb,
.reset_table = vpu_reset_tl1,
};
+static struct vpu_data_s vpu_data_sm1 = {
+ .chip_type = VPU_CHIP_SM1,
+ .chip_name = "sm1",
+ .clk_level_dft = CLK_LEVEL_DFT_G12A,
+ .clk_level_max = CLK_LEVEL_MAX_G12A,
+ .fclk_div_table = fclk_div_table_g12a,
+
+ .gp_pll_valid = 0,
+ .mem_pd_reg1_valid = 1,
+ .mem_pd_reg2_valid = 1,
+ .mem_pd_reg3_valid = 1,
+ .mem_pd_reg4_valid = 1,
+
+ .mem_pd_table_cnt =
+ sizeof(vpu_mem_pd_sm1) / sizeof(struct vpu_ctrl_s),
+ .clk_gate_table_cnt =
+ sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
+ .mem_pd_table = vpu_mem_pd_sm1,
+ .clk_gate_table = vpu_clk_gate_g12a,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+ .hdmi_iso_table = vpu_hdmi_iso_sm1,
+ .reset_table = vpu_reset_txlx,
+};
+
static const struct of_device_id vpu_of_table[] = {
{
.compatible = "amlogic, vpu-gxbb",
.compatible = "amlogic, vpu-tl1",
.data = &vpu_data_tl1,
},
+ {
+ .compatible = "amlogic, vpu-sm1",
+ .data = &vpu_data_sm1,
+ },
{},
};
VPU_CHIP_G12A,
VPU_CHIP_G12B,
VPU_CHIP_TL1,
+ VPU_CHIP_SM1,
VPU_CHIP_MAX,
};
#define VPU_REG_END 0xffff
+#define VPU_HDMI_ISO_CNT_MAX 5
#define VPU_RESET_CNT_MAX 10
struct fclk_div_s {
unsigned int module_init_table_cnt;
struct vpu_ctrl_s *module_init_table;
+ struct vpu_ctrl_s *hdmi_iso_table;
struct vpu_reset_s *reset_table;
};
{VPU_DS, HHI_VPU_MEM_PD_REG2, 0x3, 18, 2},
{VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 0x3, 20, 2},
{VPU_VIU2_OSD_ROT, HHI_VPU_MEM_PD_REG2, 0x3, 22, 2},
- {VPU_VI_DIPRE, HHI_VPU_MEM_PD_REG2, 0xf, 24, 4},
+ {VPU_DI_PRE, HHI_VPU_MEM_PD_REG2, 0xf, 24, 4},
{VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2},
{VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 0, 16},
{VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 16, 16},
{VPU_MOD_MAX, VPU_REG_END, 0, 0, 0},
};
+static struct vpu_ctrl_s vpu_mem_pd_sm1[] = {
+ /* vpu module, reg, val, bit, len */
+ {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2},
+ {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2},
+ {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2},
+ {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2},
+ {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2},
+ {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2},
+ {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2},
+ {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2},
+ {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2},
+ {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2},
+ {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2},
+ {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2},
+ {VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 24, 2},
+ {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2},
+ {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2},
+ {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2},
+ {VPU_VIU2, HHI_VPU_MEM_PD_REG1, 0xf, 0, 4},
+ {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 0x3, 4, 2},
+ {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 0x3, 6, 2},
+ {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 0x3, 8, 2},
+ {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 0x3, 10, 2},
+ {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 0x3, 12, 2},
+ {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2},
+ {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2},
+ {VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 18, 2},
+ {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2},
+ {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2},
+ {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2},
+ {VPU_LS_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2},
+ {VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2},
+ {VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2},
+ {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2},
+ {VPU_TCON, HHI_VPU_MEM_PD_REG2, 0x3, 2, 2},
+ {VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 0x3, 4, 2},
+ {VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 0x3, 6, 2},
+ {VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 0x3, 8, 2},
+ {VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 0x3, 10, 2},
+ {VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 0x3, 12, 2},
+ {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14, 2},
+ {VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 0x3, 16, 2},
+ {VPU_DS, HHI_VPU_MEM_PD_REG2, 0x3, 18, 2},
+ {VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 0x3, 20, 2},
+ {VPU_VIU2, HHI_VPU_MEM_PD_REG2, 0x3, 22, 2},
+ {VPU_DI_PRE, HHI_VPU_MEM_PD_REG2, 0xf, 24, 4},
+ {VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2},
+ {VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 0, 16},
+ {VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 16, 16},
+ {VPU_AXI_WR1, HHI_VPU_MEM_PD_REG4, 0x3, 0, 2},
+ {VPU_AXI_WR0, HHI_VPU_MEM_PD_REG4, 0x3, 2, 2},
+ {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0},
+};
+
/* ******************************************************* */
/* VPU clock gate table */
/* ******************************************************* */
};
/* ******************************************************* */
-/* VPU module init table */
+/* VPU_HDMI ISO */
+/* ******************************************************* */
+static struct vpu_ctrl_s vpu_hdmi_iso_gxb[] = {
+ /* reg, val, bit, len */
+ {AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1},
+ {VPU_REG_END, 0, 0, 0},
+};
+
+static struct vpu_ctrl_s vpu_hdmi_iso_sm1[] = {
+ /* reg, val, bit, len */
+ {AO_RTI_GEN_PWR_ISO0, 1, 8, 1},
+ {VPU_REG_END, 0, 0, 0},
+};
+
+/* ******************************************************* */
+/* VPU module init table */
/* ******************************************************* */
static struct vpu_ctrl_s vpu_module_init_gxm[] = {
/* 0, reg, val, bit, len */
};
/* ******************************************************* */
-/* VPU reset table */
+/* VPU reset table */
/* ******************************************************* */
static struct vpu_reset_s vpu_reset_gx[] = {
/* reg, mask */
"di_post",
"viu_sharpness_line_buffer",
+ "viu2",
"viu2_osd1",
"viu2_osd2",
"viu2_vd1",
"ds",
"lut3d",
"viu2_osd_rotation",
- "vi_dipre",
"rdma",
"axi_wr1",
}
/* Remove VPU_HDMI ISO */
- vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1); /* [9] VPU_HDMI */
+ ctrl_table = vpu_conf.data->hdmi_iso_table;
+ i = 0;
+ while (i < VPU_HDMI_ISO_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _bit = ctrl_table[i].bit;
+ _len = ctrl_table[i].len;
+ vpu_ao_setb(_reg, 0, _bit, _len);
+ i++;
+ }
if (vpu_debug_print_flag)
VPUPR("%s finish\n", __func__);
/* Power down VPU_HDMI */
/* Enable Isolation */
- vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1); /* ISO */
+ ctrl_table = vpu_conf.data->hdmi_iso_table;
+ while (i < VPU_HDMI_ISO_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _val = ctrl_table[i].val;
+ _bit = ctrl_table[i].bit;
+ _len = ctrl_table[i].len;
+ vpu_ao_setb(_reg, _val, _bit, _len);
+ i++;
+ }
udelay(20);
/* power down memories */
cnt = vpu_conf.data->mem_pd_table_cnt;
ctrl_table = vpu_conf.data->mem_pd_table;
+ i = 0;
while (i < cnt) {
if (ctrl_table[i].vmod == VPU_MOD_MAX)
break;
* *********************************
*/
-#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
+#define AO_RTI_GEN_PWR_SLEEP0 (0x03a << 2)
+#define AO_RTI_GEN_PWR_ISO0 (0x03b << 2)
/* HHI bus */
#define HHI_GP1_PLL_CNTL 0x16
/* VPU module define */
/* ************************************************ */
enum vpu_mod_e {
- VPU_VIU_OSD1 = 0, /* reg0[1:0] //common */
- VPU_VIU_OSD2, /* reg0[3:2] //common */
- VPU_VIU_VD1, /* reg0[5:4] //common */
- VPU_VIU_VD2, /* reg0[7:6] //common */
- VPU_VIU_CHROMA, /* reg0[9:8] //common */
- VPU_VIU_OFIFO, /* reg0[11:10] //common */
- VPU_VIU_SCALE, /* reg0[13:12] //common */
- VPU_VIU_OSD_SCALE, /* reg0[15:14] //common */
- VPU_VIU_VDIN0, /* reg0[17:16] //common */
- VPU_VIU_VDIN1, /* reg0[19:18] //common */
- VPU_VIU_SRSCL, /* reg0[21:20] //GXBB, GXTVBB, TXLX */
- VPU_VIU_OSDSR, /* reg0[23:22] //GXBB */
- VPU_AFBC_DEC1, /* reg0[23:22] //GXTVBB, TXLX */
- VPU_VIU_DI_SCALE, /* reg0[25:24] //G12A */
- VPU_DI_PRE, /* reg0[27:26] //common */
- VPU_DI_POST, /* reg0[29:28] //common */
- VPU_SHARP, /* reg0[31:30] //common */
+ VPU_VIU_OSD1 = 0, /* reg0[1:0], common */
+ VPU_VIU_OSD2, /* reg0[3:2], common */
+ VPU_VIU_VD1, /* reg0[5:4], common */
+ VPU_VIU_VD2, /* reg0[7:6], common */
+ VPU_VIU_CHROMA, /* reg0[9:8], common */
+ VPU_VIU_OFIFO, /* reg0[11:10], common */
+ VPU_VIU_SCALE, /* reg0[13:12], common */
+ VPU_VIU_OSD_SCALE, /* reg0[15:14], common */
+ VPU_VIU_VDIN0, /* reg0[17:16], common */
+ VPU_VIU_VDIN1, /* reg0[19:18], common */
+ VPU_VIU_SRSCL, /* reg0[21:20], GXBB, GXTVBB, TXLX */
+ VPU_VIU_OSDSR, /* reg0[23:22], GXBB */
+ VPU_AFBC_DEC1, /* reg0[23:22], GXTVBB, TXLX */
+ VPU_VIU_DI_SCALE, /* reg0[25:24], G12A */
+ VPU_DI_PRE, /* reg0[27:26], common */
+ VPU_DI_POST, /* reg0[29:28], common */
+ VPU_SHARP, /* reg0[31:30], common */
+ VPU_VIU2, /* reg1[3:0], reg2[23:22], SM1 */
VPU_VIU2_OSD1, /* reg1[1:0] */
VPU_VIU2_OSD2, /* reg1[3:2] */
VPU_VIU2_VD1, /* reg1[5:4] */
VPU_VIU2_OFIFO, /* reg1[9:8] */
VPU_VIU2_SCALE, /* reg1[11:10] */
VPU_VIU2_OSD_SCALE, /* reg1[13:12] */
- VPU_VKSTONE, /* reg1[5:4] //TXLX */
- VPU_DOLBY_CORE3, /* reg1[7:6] //TXLX */
- VPU_DOLBY0, /* reg1[9:8] //TXLX */
- VPU_DOLBY1A, /* reg1[11:10] //TXLX */
- VPU_DOLBY1B, /* reg1[13:12] //TXLX */
- VPU_VPU_ARB, /* reg1[15:14] //GXBB, GXTVBB, GXL, TXLX */
- VPU_AFBC_DEC, /* reg1[17:16] //GXBB, GXTVBB, TXL, TXLX */
- VPU_OSD_AFBCD, /* reg1[19:18] //TXLX */
- VPU_VD2_SCALE, /* reg1[19:18] //G12A */
- VPU_VENCP, /* reg1[21:20] //common */
- VPU_VENCL, /* reg1[23:22] //common */
- VPU_VENCI, /* reg1[25:24] //common */
- VPU_LS_STTS, /* reg1[27:26] //tl1 */
- VPU_LDIM_STTS, /* reg1[29:28] //GXTVBB, GXL, TXL, TXLX */
+ VPU_VKSTONE, /* reg1[5:4], TXLX */
+ VPU_DOLBY_CORE3, /* reg1[7:6], TXLX */
+ VPU_DOLBY0, /* reg1[9:8], TXLX */
+ VPU_DOLBY1A, /* reg1[11:10], TXLX */
+ VPU_DOLBY1B, /* reg1[13:12], TXLX */
+ VPU_VPU_ARB, /* reg1[15:14], GXBB, GXTVBB, GXL, TXLX */
+ VPU_AFBC_DEC, /* reg1[17:16], GXBB, GXTVBB, TXL, TXLX */
+ VPU_OSD_AFBCD, /* reg1[19:18], TXLX */
+ VPU_VD2_SCALE, /* reg1[19:18], G12A */
+ VPU_VENCP, /* reg1[21:20], common */
+ VPU_VENCL, /* reg1[23:22], common */
+ VPU_VENCI, /* reg1[25:24], common */
+ VPU_LS_STTS, /* reg1[27:26], tl1 */
+ VPU_LDIM_STTS, /* reg1[29:28], GXTVBB, GXL, TXL, TXLX */
VPU_TV_DEC_CVD2, /* reg1[29:28] */
- VPU_XVYCC_LUT, /* reg1[31:30] //GXTVBB, GXL, TXL, TXLX */
- VPU_VD2_OSD2_SCALE, /* reg1[31:30] //G12A */
+ VPU_XVYCC_LUT, /* reg1[31:30], GXTVBB, GXL, TXL, TXLX */
+ VPU_VD2_OSD2_SCALE, /* reg1[31:30], G12A */
- VPU_VIU_WM, /* reg2[1:0] //GXL, TXL, TXLX */
- VPU_TCON, /* reg2[3:2] //TXHD, TL1 */
- VPU_VIU_OSD3, /* reg2[5:4] //G12A */
- VPU_VIU_OSD4, /* reg2[7:6] //G12A */
- VPU_MAIL_AFBCD, /* reg2[9:8] //G12A */
- VPU_VD1_SCALE, /* reg2[11:10] //G12A */
- VPU_OSD_BLD34, /* reg2[13:12] //G12A */
- VPU_PRIME_DOLBY_RAM, /* reg2[15:14] //G12A */
- VPU_VD2_OFIFO, /* reg2[17:16] //G12A */
- VPU_DS, /* reg2[19:18] //TL1 */
- VPU_LUT3D, /* reg2[21:20] //G12B */
- VPU_VIU2_OSD_ROT, /* reg2[23:22] //G12B */
- VPU_VI_DIPRE, /* reg2[27:24] //TL1 */
- VPU_RDMA, /* reg2[31:30] //G12A */
+ VPU_VIU_WM, /* reg2[1:0], GXL, TXL, TXLX */
+ VPU_TCON, /* reg2[3:2], TXHD, TL1 */
+ VPU_VIU_OSD3, /* reg2[5:4], G12A */
+ VPU_VIU_OSD4, /* reg2[7:6], G12A */
+ VPU_MAIL_AFBCD, /* reg2[9:8], G12A */
+ VPU_VD1_SCALE, /* reg2[11:10], G12A */
+ VPU_OSD_BLD34, /* reg2[13:12], G12A */
+ VPU_PRIME_DOLBY_RAM, /* reg2[15:14], G12A */
+ VPU_VD2_OFIFO, /* reg2[17:16], G12A */
+ VPU_DS, /* reg2[19:18], TL1 */
+ VPU_LUT3D, /* reg2[21:20], G12B */
+ VPU_VIU2_OSD_ROT, /* reg2[23:22], G12B */
+ VPU_RDMA, /* reg2[31:30], G12A */
- VPU_AXI_WR1, /* reg4[1:0] //TL1 */
- VPU_AXI_WR0, /* reg4[3:2] //TL1 */
- VPU_AFBCE, /* reg4[5:4] //TL1 */
+ VPU_AXI_WR1, /* reg4[1:0], TL1 */
+ VPU_AXI_WR0, /* reg4[3:2], TL1 */
+ VPU_AFBCE, /* reg4[5:4], TL1 */
VPU_MOD_MAX,
projects / platform / kernel / linux-amlogic.git / commitdiff