wifi: rtw89: release RX standby timer of beamformee CSI to save power
authorPing-Ke Shih <pkshih@realtek.com>
Tue, 7 Mar 2023 14:18:48 +0000 (22:18 +0800)
committerKalle Valo <kvalo@kernel.org>
Mon, 13 Mar 2023 13:43:39 +0000 (15:43 +0200)
Originally, we keep RX standby timer to handle beamformee CSI, but this
spends power and causes system not entering power save mode. To improve
power consumption, release the timer if throughput becomes low.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230307141848.26403-1-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/reg.h

index b1a886898c5a088cd5459c7e753543997b864972..9073f526b5a3c94833a62d73ed374cc5160297a7 100644 (file)
@@ -3168,6 +3168,7 @@ enum rtw89_flags {
        RTW89_FLAG_RUNNING,
        RTW89_FLAG_BFEE_MON,
        RTW89_FLAG_BFEE_EN,
+       RTW89_FLAG_BFEE_TIMER_KEEP,
        RTW89_FLAG_NAPI_RUNNING,
        RTW89_FLAG_LEISURE_PS,
        RTW89_FLAG_LOW_POWER_MODE,
index 3d1e4ffef1b16c1d9456a93837f8833a33e6be8a..7866fe925d2484cb46012dec0532ef3fb39959f9 100644 (file)
@@ -4931,6 +4931,24 @@ u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
        return cnt;
 }
 
+static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,
+                                        bool keep)
+{
+       u32 reg;
+
+       rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);
+       reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);
+       if (keep) {
+               set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
+               rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
+                                  BFRP_RX_STANDBY_TIMER_KEEP);
+       } else {
+               clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
+               rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
+                                  BFRP_RX_STANDBY_TIMER_RELEASE);
+       }
+}
+
 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
 {
        u32 reg;
@@ -4967,9 +4985,9 @@ static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)
        rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
 
        reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);
-       val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER);
-       val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER);
+       val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER);
        rtw89_write32(rtwdev, reg, val32);
+       rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);
        rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
 
        reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
@@ -5181,6 +5199,19 @@ void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
        struct rtw89_vif *rtwvif;
        bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv;
        bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
+       bool keep_timer = true;
+       bool old_keep_timer;
+
+       old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
+
+       if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW)
+               keep_timer = false;
+
+       if (keep_timer != old_keep_timer) {
+               rtw89_for_each_rtwvif(rtwdev, rtwvif)
+                       rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx,
+                                                    keep_timer);
+       }
 
        if (en == old)
                return;
index 600257909df274847803a61a29ae97d032f6129f..e5c0ab43ab7a02b045e85ed1373c25b624c9d808 100644 (file)
 #define R_AX_BFMEE_RESP_OPTION_C1 0xED80
 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
 #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
+#define BFRP_RX_STANDBY_TIMER_KEEP 0x0
+#define BFRP_RX_STANDBY_TIMER_RELEASE 0x1
 #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
 #define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16)
 #define BFRP_RX_STANDBY_TIMER          0x0