[x86] add tests for basic logic op folds

llvm-svn: 285520

diff --git a/llvm/test/CodeGen/X86/combine-and.ll b/llvm/test/CodeGen/X86/combine-and.ll
index 2170910..8ff8ebb 100644 (file)
--- a/llvm/test/CodeGen/X86/combine-and.ll
+++ b/llvm/test/CodeGen/X86/combine-and.ll
@@ -1,6 +1,25 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s
 
+define i32 @and_self(i32 %x) {
+; CHECK-LABEL: and_self:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    andl %edi, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %and = and i32 %x, %x
+  ret i32 %and
+}
+
+define <4 x i32> @and_self_vec(<4 x i32> %x) {
+; CHECK-LABEL: and_self_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    andps %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %and = and <4 x i32> %x, %x
+  ret <4 x i32> %and
+}
+
 ;
 ; Verify that the DAGCombiner is able to fold a vector AND into a blend
 ; if one of the operands to the AND is a vector of all constants, and each

diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll
index f674ddd..bc439de 100644 (file)
--- a/llvm/test/CodeGen/X86/combine-or.ll
+++ b/llvm/test/CodeGen/X86/combine-or.ll
@@ -1,6 +1,24 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
 
+define i32 @or_self(i32 %x) {
+; CHECK-LABEL: or_self:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    orl %edi, %edi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
+  %or = or i32 %x, %x
+  ret i32 %or
+}
+
+define <4 x i32> @or_self_vec(<4 x i32> %x) {
+; CHECK-LABEL: or_self_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    orps %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %or = or <4 x i32> %x, %x
+  ret <4 x i32> %or
+}
 
 ; Verify that each of the following test cases is folded into a single
 ; instruction which performs a blend operation.