ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogs

Even though upstream Linux doesn't yet go into deep enough suspend to
get DDR into self refresh, there is no harm in setting these pins up.
They'll only actually do something if we go into a deeper suspend but
leaving them configed always is fine.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index 72c4754..b9cc90f 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -229,6 +229,8 @@
 &pinctrl {
        pinctrl-0 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
 
                /* Wake only */
@@ -236,6 +238,8 @@
        >;
        pinctrl-1 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
 
                /* Sleep only */

diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index e4f0c00..3575587 100644 (file)
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -453,10 +453,14 @@
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
        >;
        pinctrl-1 = <
                /* Common for sleep and wake, but no owners */
+               &ddr0_retention
+               &ddrio_pwroff
                &global_pwroff
        >;