ret float %i3
}
+define float @v_fmul_0_fsub_0_infloop_regression(float %arg) {
+; GCN-SAFE-LABEL: v_fmul_0_fsub_0_infloop_regression:
+; GCN-SAFE: ; %bb.0: ; %bb
+; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SAFE-NEXT: v_mul_f32_e32 v0, 0, v0
+; GCN-SAFE-NEXT: v_sub_f32_e32 v0, 0, v0
+; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
+;
+; GCN-NSZ-LABEL: v_fmul_0_fsub_0_infloop_regression:
+; GCN-NSZ: ; %bb.0: ; %bb
+; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NSZ-NEXT: v_mul_f32_e32 v0, 0x80000000, v0
+; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
+bb:
+ %i = fmul float %arg, 0.0
+ %i1 = fsub float 0.0, %i
+ ret float %i1
+}
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.fma.f32(float, float, float) #1
declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)