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cpufreq: dynamic adjustment dsu clk with tl1 cpu clk [1/3]
authorHong Guo <hong.guo@amlogic.com>
Thu, 21 Feb 2019 07:21:08 +0000 (15:21 +0800)
committerTao Zeng <tao.zeng@amlogic.com>
Fri, 26 Apr 2019 10:12:01 +0000 (03:12 -0700)
PD#SWPL-2842

Problem:
dynamic adjustment dsu clk with cpu clk.

Solution:
dynamic adjustment dsu clk with cpu clk.

Verify:
tl1_x301, verify pass

Change-Id: I75f97d9e259dee2c3067e5989b3626e38cf20337
Signed-off-by: Hong Guo <hong.guo@amlogic.com>
12 files changed:
arch/arm/boot/dts/amlogic/mesontl1.dtsi patch | blob | history
arch/arm/boot/dts/amlogic/tl1_pxp.dts patch | blob | history
arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts patch | blob | history
arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts patch | blob | history
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts patch | blob | history
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts patch | blob | history
arch/arm64/boot/dts/amlogic/mesontl1.dtsi patch | blob | history
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts patch | blob | history
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts patch | blob | history
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts patch | blob | history
drivers/amlogic/cpufreq/meson-cpufreq.c patch | blob | history
drivers/amlogic/cpufreq/meson-cpufreq.h patch | blob | history

diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi
index b64e30a..c08e74f 100644 (file)
--- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi
+++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi
@@ -43,10 +43,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
@@ -62,10 +66,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
@@ -81,10 +89,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
@@ -100,10 +112,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
index 7f19bdf..2f14806 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
@@ -566,7 +566,6 @@
                reg-names = "ao_exit","ao";
        };
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
index 200a2ca..6ea7d95 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
@@ -1066,58 +1066,57 @@
                };
        };/*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
 
                opp00 {
                        opp-hz = /bits/ 64 <100000000>;
-                       opp-microvolt = <699000>;
+                       opp-microvolt = <729000>;
                };
                opp01 {
                        opp-hz = /bits/ 64 <250000000>;
-                       opp-microvolt = <699000>;
+                       opp-microvolt = <729000>;
                };
                opp02 {
                        opp-hz = /bits/ 64 <500000000>;
-                       opp-microvolt = <709000>;
+                       opp-microvolt = <729000>;
                };
                opp03 {
                        opp-hz = /bits/ 64 <667000000>;
-                       opp-microvolt = <719000>;
+                       opp-microvolt = <749000>;
                };
                opp04 {
                        opp-hz = /bits/ 64 <1000000000>;
-                       opp-microvolt = <729000>;
+                       opp-microvolt = <769000>;
                };
                opp05 {
                        opp-hz = /bits/ 64 <1200000000>;
-                       opp-microvolt = <749000>;
+                       opp-microvolt = <779000>;
                };
                opp06 {
                        opp-hz = /bits/ 64 <1404000000>;
-                       opp-microvolt = <769000>;
+                       opp-microvolt = <789000>;
                };
                opp07 {
                        opp-hz = /bits/ 64 <1500000000>;
-                       opp-microvolt = <779000>;
+                       opp-microvolt = <799000>;
                };
                opp08 {
                        opp-hz = /bits/ 64 <1608000000>;
-                       opp-microvolt = <789000>;
+                       opp-microvolt = <809000>;
                };
                opp09 {
                        opp-hz = /bits/ 64 <1704000000>;
-                       opp-microvolt = <829000>;
+                       opp-microvolt = <849000>;
                };
                opp10 {
                        opp-hz = /bits/ 64 <1800000000>;
-                       opp-microvolt = <879000>;
+                       opp-microvolt = <899000>;
                };
                opp11 {
                        opp-hz = /bits/ 64 <1908000000>;
-                       opp-microvolt = <929000>;
+                       opp-microvolt = <949000>;
                };
        };
 
diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
index 3be54a2..40a8bae 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
@@ -1078,7 +1078,6 @@
                };
        }; /*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
index 51b19b8..1e66516 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
@@ -1102,7 +1102,6 @@
                };
        }; /*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
index f2c61ce..45e143b 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
@@ -1097,7 +1097,6 @@
                };
        }; /*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/arch/arm64/boot/dts/amlogic/mesontl1.dtsi b/arch/arm64/boot/dts/amlogic/mesontl1.dtsi
index b8cf37f..87422e0 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/mesontl1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesontl1.dtsi
@@ -43,10 +43,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
@@ -62,10 +66,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
@@ -81,10 +89,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
@@ -100,10 +112,14 @@
                        enable-method = "psci";
                        clocks = <&clkc CLKID_CPU_CLK>,
                                <&clkc CLKID_CPU_FCLK_P>,
-                               <&clkc CLKID_SYS_PLL>;
+                               <&clkc CLKID_SYS_PLL>,
+                               <&clkc CLKID_DSU_CLK>,
+                               <&clkc CLKID_DSU_PRE_CLK>;
                        clock-names = "core_clk",
                                "low_freq_clk_parent",
-                               "high_freq_clk_parent";
+                               "high_freq_clk_parent",
+                               "dsu_clk",
+                               "dsu_pre_parent";
                        operating-points-v2 = <&cpu_opp_table0>;
                        cpu-supply = <&vddcpu0>;
                        //cpu-idle-states = <&SYSTEM_SLEEP_0>;
diff --git a/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts b/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
index c3311cb..a171e51 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
@@ -1076,7 +1076,6 @@
                };
        }; /*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
index 42dc9a1..95e41d0 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
@@ -1098,7 +1098,6 @@
                };
        }; /*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
index d516c30..05788b9 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
@@ -1092,7 +1092,6 @@
                };
        }; /*thermal zone end*/
 
-       /*DCDC for MP8756GD*/
        cpu_opp_table0: cpu_opp_table0 {
                compatible = "operating-points-v2";
                opp-shared;
diff --git a/drivers/amlogic/cpufreq/meson-cpufreq.c b/drivers/amlogic/cpufreq/meson-cpufreq.c
index 890b86f..996b63b 100644 (file)
--- a/drivers/amlogic/cpufreq/meson-cpufreq.c
+++ b/drivers/amlogic/cpufreq/meson-cpufreq.c
@@ -397,44 +397,52 @@ static int meson_cpufreq_transition_notifier(struct notifier_block *nb,
        struct clk *dsu_cpu_parent =  policy->clk;
        struct clk *dsu_pre_parent = cpufreq_data->clk_dsu_pre;
        int ret = 0;
-       static bool first_set = true;
+       unsigned int dsu_set_rate;
 
        if (!dsu_clk || !dsu_cpu_parent || !dsu_pre_parent)
                return 0;
 
-       pr_debug("%s,event %ld,freq->old_rate =%u,freq->new_rate =%u!\n",
+       pr_debug("%s:event %ld,old_rate =%u,new_rate =%u!\n",
                __func__, val, freq->old, freq->new);
        switch (val) {
        case CPUFREQ_PRECHANGE:
-               if (freq->new > MID_RATE) {
-                       pr_debug("%s,dsu clk switch parent to dsu pre!\n",
+               if (freq->new > DSU_LOW_RATE) {
+                       pr_debug("%s:dsu clk switch parent to dsu pre!\n",
                                __func__);
-                       if (first_set) {
-                               clk_set_rate(dsu_pre_parent, MID_RATE * 1000);
-                               first_set = false;
-                               pr_info("first set gp1 pll to 1.5G!\n");
-                       }
                        if (__clk_get_enable_count(dsu_pre_parent) == 0) {
                                ret = clk_prepare_enable(dsu_pre_parent);
                                if (ret) {
-                                       pr_err("%s: CPU%d gp1 pll enable failed\n",
-                                                       __func__, policy->cpu);
+                                       pr_err("%s: CPU%d gp1 pll enable failed,ret = %d\n",
+                                               __func__, policy->cpu, ret);
                                        return ret;
                                }
                        }
 
+                       if (freq->new > CPU_CMP_RATE)
+                               dsu_set_rate = DSU_HIGH_RATE;
+                       else
+                               dsu_set_rate = DSU_LOW_RATE;
+
+                       clk_set_rate(dsu_pre_parent, dsu_set_rate * 1000);
+                       if (ret) {
+                               pr_err("%s: GP1 clk setting %u MHz failed, ret = %d!\n",
+                                       __func__, dsu_set_rate, ret);
+                               return ret;
+                       }
+                       pr_debug("%s:GP1 clk setting %u MHz!\n",
+                               __func__, dsu_set_rate);
+
                        ret = clk_set_parent(dsu_clk, dsu_pre_parent);
                }
 
                return ret;
        case CPUFREQ_POSTCHANGE:
-               if (freq->new <= MID_RATE) {
-                       pr_debug("%s,dsu clk switch parent to cpu!\n",
+               if (freq->new <= DSU_LOW_RATE) {
+                       pr_debug("%s:dsu clk switch parent to cpu!\n",
                                __func__);
                        ret = clk_set_parent(dsu_clk, dsu_cpu_parent);
                        if (__clk_get_enable_count(dsu_pre_parent) >= 1)
                                clk_disable_unprepare(dsu_pre_parent);
-
                }
 
                return ret;
@@ -525,13 +533,13 @@ static int meson_cpufreq_init(struct cpufreq_policy *policy)
        dsu_clk = of_clk_get_by_name(np, DSU_CLK);
        if (IS_ERR(dsu_clk)) {
                dsu_clk = NULL;
-               pr_debug("%s: ignor dsu clk!\n", __func__);
+               pr_info("%s: ignor dsu clk!\n", __func__);
        }
 
        dsu_pre_parent = of_clk_get_by_name(np, DSU_PRE_PARENT);
        if (IS_ERR(dsu_pre_parent)) {
                dsu_pre_parent = NULL;
-               pr_debug("%s: ignor dsu pre parent clk!\n", __func__);
+               pr_info("%s: ignor dsu pre parent clk!\n", __func__);
        }
 
        cpu_reg = devm_regulator_get(cpu_dev, CORE_SUPPLY);
diff --git a/drivers/amlogic/cpufreq/meson-cpufreq.h b/drivers/amlogic/cpufreq/meson-cpufreq.h
index d5508c5..09d6b2e 100644 (file)
--- a/drivers/amlogic/cpufreq/meson-cpufreq.h
+++ b/drivers/amlogic/cpufreq/meson-cpufreq.h
@@ -43,7 +43,19 @@ static struct cpufreq_frequency_table *freq_table[MAX_CLUSTERS];
 static unsigned int mid_rate = (1000 * 1000);
 static unsigned int gap_rate = (10 * 1000 * 1000);
 static struct cpufreq_freqs freqs;
-#define MID_RATE (1500 * 1000)
+
+/*
+ * DSU_LOW_RATE:cpu clk less than DSU_LOW_RATE(1.2G)
+ * dsu clk swith to cpu clk
+ * DSU_HIGH_RATE:cpu clk between 1.2G to DSU_HIGH_RATE (1.8G)
+ * dsu clk set to DSU_LOW_RATE(1.2G)
+ * CPU_CMP_RATE: cpu clk greater than CPU_CMP_RATE(1.8G)
+ * dsu clk set to DSU_HIGH_RATE(1.5G)
+ */
+
+#define DSU_LOW_RATE (1200 * 1000)
+#define DSU_HIGH_RATE (1500 * 1000)
+#define CPU_CMP_RATE (1800 * 1000)
 
 /*whether use different tables or not*/
 bool cpufreq_tables_supply;
Domain: System / Kernel;