This patch is preliminary for 64bit BAR.
Later pcibus_t will be changed from uint32_t to uint64_t.
Introduce FMT_PCIBUS for printf format for pcibus_t.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
pcibus_t size, int type)
{
- DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
+ DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
+ " size=0x%08"FMT_PCIBUS"\n", addr, size);
}
static void
};
- DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
+ DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
+ addr, size);
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
qemu_register_coalesced_mmio(addr, excluded_regs[0]);
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
- TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
+ TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
+ "size=0x%08"FMT_PCIBUS", type=%d\n",
region_num, addr, size, type));
assert(region_num == 1);
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
- TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
+ TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
+ "size=0x%08"FMT_PCIBUS", type=%d\n",
region_num, addr, size, type));
if (region_num == 0) {
if (size & (size-1)) {
fprintf(stderr, "ERROR: PCI region size must be pow2 "
- "type=0x%x, size=0x%x\n", type, size);
+ "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
exit(1);
}
wmask |= PCI_ROM_ADDRESS_ENABLE;
}
pci_set_long(pci_dev->config + addr, type);
- pci_set_long(pci_dev->wmask + addr, wmask);
+ pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
}
if (r->size != 0) {
monitor_printf(mon, " BAR%d: ", i);
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
- monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
+ monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
+ " [0x%04"FMT_PCIBUS"].\n",
r->addr, r->addr + r->size - 1);
} else {
- monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
+ monitor_printf(mon, "32 bit memory at 0x%08"FMT_PCIBUS
+ " [0x%08"FMT_PCIBUS"].\n",
r->addr, r->addr + r->size - 1);
}
}
r = &d->io_regions[i];
if (!r->size)
continue;
- monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
+ monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
+ " [0x%"FMT_PCIBUS"]\n",
+ indent, "",
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
r->addr, r->addr + r->size - 1);
}
#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
typedef uint32_t pcibus_t;
+#define FMT_PCIBUS PRIx32
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
uint32_t address, uint32_t data, int len);
PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state;
#ifdef PCNET_DEBUG_IO
- printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
+ printf("pcnet_ioport_map addr=0x%04"FMT_PCIBUS" size=0x%04"FMT_PCIBUS"\n",
+ addr, size);
#endif
register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
#ifdef PCNET_DEBUG_IO
- printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);
+ printf("pcnet_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
+ addr, size);
#endif
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index);
I6300State *d = DO_UPCAST(I6300State, dev, dev);
int io_mem;
- i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);
+ i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n",
+ addr, size, type);
io_mem = cpu_register_io_memory(mem_read, mem_write, d);
cpu_register_physical_memory (addr, 0x10, io_mem);