[AArch64][GlobalISel] Fix fallbacks introduced for G_SITOFP in 8f283cafddfa8d6d01a94b...
authorAmara Emerson <amara@apple.com>
Fri, 15 Jan 2021 08:57:51 +0000 (00:57 -0800)
committerAmara Emerson <amara@apple.com>
Fri, 15 Jan 2021 09:10:49 +0000 (01:10 -0800)
If we have an integer->fp convert that has differing sizes, e.g. s32 to s64,
then don't try to convert it to AArch64::G_SITOF since it won't select.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

index 5dcb9b2..797f33c 100644 (file)
@@ -1947,8 +1947,11 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
     // Otherwise, it ends up matching an fpr/gpr variant and adding a cross-bank
     // copy.
     Register SrcReg = I.getOperand(1).getReg();
-    if (MRI.getType(SrcReg).isVector())
+    LLT SrcTy = MRI.getType(SrcReg);
+    LLT DstTy = MRI.getType(I.getOperand(0).getReg());
+    if (SrcTy.isVector() || SrcTy.getSizeInBits() != DstTy.getSizeInBits())
       return false;
+
     if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) {
       if (I.getOpcode() == TargetOpcode::G_SITOFP)
         I.setDesc(TII.get(AArch64::G_SITOF));
index aad71bd..4274f91 100644 (file)
@@ -328,6 +328,29 @@ body:             |
 ...
 
 ---
+name:            sitofp_s64_s32_fpr_both
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $s0
+
+    ; CHECK-LABEL: name: sitofp_s64_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY2]]
+    ; CHECK: $d0 = COPY [[SCVTFUWDri]]
+    %0(s32) = COPY $s0
+    %1(s64) = G_SITOFP %0
+    $d0 = COPY %1(s64)
+...
+
+---
 name:            sitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true