arm64: dts: renesas: hihope-common: Add HDMI support
authorFabrizio Castro <fabrizio.castro@bp.renesas.com>
Tue, 18 Jun 2019 15:18:39 +0000 (16:18 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 19 Jun 2019 14:04:03 +0000 (16:04 +0200)
Add HDMI support to the HiHope RZ/G2[MN] mother board common
dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/hihope-common.dtsi

index 625c3aa..9f05e80 100644 (file)
                stdout-path = "serial0:115200n8";
        };
 
+       hdmi0-out {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi0_con: endpoint {
+                               remote-endpoint = <&rcar_dw_hdmi0_out>;
+                       };
+               };
+       };
+
        leds {
                compatible = "gpio-leds";
 
                states = <3300000 1
                          1800000 0>;
        };
+
+       x302_clk: x302-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <33000000>;
+       };
+
+       x304_clk: x304-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+};
+
+&du {
+       clocks = <&cpg CPG_MOD 724>,
+                <&cpg CPG_MOD 723>,
+                <&cpg CPG_MOD 722>,
+                <&versaclock5 1>,
+                <&x302_clk>,
+                <&versaclock5 2>;
+       clock-names = "du.0", "du.1", "du.2",
+                     "dclkin.0", "dclkin.1", "dclkin.2";
+       status = "okay";
 };
 
 &ehci0 {
        };
 };
 
+&hdmi0 {
+       status = "okay";
+
+       ports {
+               port@1 {
+                       reg = <1>;
+                       rcar_dw_hdmi0_out: endpoint {
+                               remote-endpoint = <&hdmi0_con>;
+                       };
+               };
+       };
+};
+
 &hsusb {
        dr_mode = "otg";
        status = "okay";
 };
 
+&i2c4 {
+       clock-frequency = <400000>;
+       status = "okay";
+
+       versaclock5: clock-generator@6a {
+               compatible = "idt,5p49v5923";
+               reg = <0x6a>;
+               #clock-cells = <1>;
+               clocks = <&x304_clk>;
+               clock-names = "xin";
+       };
+};
+
 &ohci0 {
        status = "okay";
 };