Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
authorWolfgang Denk <wd@denx.de>
Fri, 12 Dec 2008 23:36:25 +0000 (00:36 +0100)
committerWolfgang Denk <wd@denx.de>
Fri, 12 Dec 2008 23:36:25 +0000 (00:36 +0100)
Makefile
board/esd/cpci405/config.mk
board/esd/pmc440/pmc440.c
include/configs/CPCI405.h
include/configs/alpr.h

index 7ef7df9..d6cd91a 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1261,14 +1261,11 @@ CMS700_config:  unconfig
 CPCI2DP_config:        unconfig
        @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
 
-CPCI405_config:                unconfig
-       @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
-
+CPCI405_config         \
 CPCI4052_config                \
 CPCI405DT_config       \
 CPCI405AB_config:      unconfig
        @mkdir -p $(obj)board/esd/cpci405
-       @echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
        @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
 
 CPCIISER4_config:      unconfig
index 6cfb891..1bdf5e4 100644 (file)
@@ -21,8 +21,4 @@
 # MA 02111-1307 USA
 #
 
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFD0000
-endif
+TEXT_BASE = 0xFFFC0000
index 8563d7d..3824105 100644 (file)
@@ -107,7 +107,7 @@ int board_early_init_f(void)
         * Setup the GPIO pins
         * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
         */
-       out32(GPIO0_OR,    0x40000002);
+       out32(GPIO0_OR,    0x40000102);
        out32(GPIO0_TCR,   0x4c90011f);
        out32(GPIO0_OSRL,  0x28051400);
        out32(GPIO0_OSRH,  0x55005000);
@@ -755,17 +755,31 @@ int post_hotkeys_pressed(void)
 #ifdef CONFIG_RESET_PHY_R
 void reset_phy(void)
 {
+       char *s;
+       unsigned short val_method, val_behavior;
+
+       /* special LED setup for NGCC/CANDES */
+       if ((s = getenv("bd_type")) &&
+           ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
+               val_method   = 0x0e0a;
+               val_behavior = 0x0cf2;
+       } else {
+               /* PMC440 standard type */
+               val_method   = 0x0e10;
+               val_behavior = 0x0cf0;
+       }
+
        if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
                miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
-               miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
-               miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
+               miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
+               miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
                miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
        }
 
        if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
                miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
-               miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
-               miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
+               miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
+               miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
                miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
        }
 }
index 1a2bc1c..89ba139 100644 (file)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_FLASH_BASE          0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN         (192 * 1024)    /* Reserve 196 kB for Monitor   */
+#define CONFIG_SYS_FLASH_BASE          TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (~(TEXT_BASE) + 1)
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 
 /*
index 6e9f5e5..7ce8205 100644 (file)
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
 #define CONFIG_CMD_FPGA
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
+#undef CONFIG_CMD_NFS
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */