regulator: rtmv20: Update DT binding document and property name parsing

1. Add vendor suffix to all proprietary properties.
2. Fix typo.
3. Change lsw to normal property, not pattern property.
4. Due to item 1, modify source code for property parsing.

Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
Link: https://lore.kernel.org/r/1601460480-4259-1-git-send-email-u0084500@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/regulator/richtek,rtmv20-regulator.yaml b/Documentation/devicetree/bindings/regulator/richtek,rtmv20-regulator.yaml
index 4cb4b68..a8ccb5c 100644 (file)
--- a/Documentation/devicetree/bindings/regulator/richtek,rtmv20-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/richtek,rtmv20-regulator.yaml
@@ -26,108 +26,99 @@ properties:
 
   wakeup-source: true
 
-  interrupts-extend:
+  interrupts:
     maxItems: 1
 
   enable-gpios:
     description: A connection of the 'enable' gpio line.
     maxItems: 1
 
-  ld-pulse-delay-us:
+  richtek,ld-pulse-delay-us:
     description: |
       load current pulse delay in microsecond after strobe pin pulse high.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 0
     maximum: 100000
     default: 0
 
-  ld-pulse-width-us:
+  richtek,ld-pulse-width-us:
     description: |
       Load current pulse width in microsecond after strobe pin pulse high.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 0
     maximum: 10000
     default: 1200
 
-  fsin1-delay-us:
+  richtek,fsin1-delay-us:
     description: |
       Fsin1 pulse high delay in microsecond after vsync signal pulse high.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 0
     maximum: 100000
     default: 23000
 
-  fsin1-width-us:
+  richtek,fsin1-width-us:
     description: |
       Fsin1 pulse high width in microsecond after vsync signal pulse high.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 40
     maximum: 10000
     default: 160
 
-  fsin2-delay-us:
+  richtek,fsin2-delay-us:
     description: |
       Fsin2 pulse high delay in microsecond after vsync signal pulse high.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 0
     maximum: 100000
     default: 23000
 
-  fsin2-width-us:
+  richtek,fsin2-width-us:
     description: |
       Fsin2 pulse high width in microsecond after vsync signal pulse high.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 40
     maximum: 10000
     default: 160
 
-  es-pulse-width-us:
+  richtek,es-pulse-width-us:
     description: Eye safety function pulse width limit in microsecond.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 0
     maximum: 10000
     default: 1200
 
-  es-ld-current-microamp:
+  richtek,es-ld-current-microamp:
     description: Eye safety function load current limit in microamp.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 0
     maximum: 6000000
     default: 3000000
 
-  lbp-level-microvolt:
+  richtek,lbp-level-microvolt:
     description: Low battery protection level in microvolt.
-    $ref: "/schemas/types.yaml#/definitions/uint32"
     minimum: 2400000
     maximum: 3700000
     default: 2700000
 
-  lbp-enable:
+  richtek,lbp-enable:
     description: Low battery protection function enable control.
     type: boolean
 
-  strobe-polarity-high:
+  richtek,strobe-polarity-high:
     description: Strobe pin active polarity control.
     type: boolean
 
-  vsync-polarity-high:
+  richtek,vsync-polarity-high:
     description: Vsync pin active polarity control.
     type: boolean
 
-  fsin-enable:
+  richtek,fsin-enable:
     description: Fsin function enable control.
     type: boolean
 
-  fsin-output:
+  richtek,fsin-output:
     description: Fsin function output control.
     type: boolean
 
-  es-enable:
+  richtek,es-enable:
     description: Eye safety function enable control.
     type: boolean
 
-patternProperties:
-  "lsw":
+  lsw:
+    description: load switch current regulator description.
     type: object
     $ref: "regulator.yaml#"
 
@@ -135,7 +126,7 @@ required:
   - compatible
   - reg
   - wakeup-source
-  - interrupts-extend
+  - interrupts
   - enable-gpios
   - lsw
 
@@ -152,11 +143,11 @@ examples:
         compatible = "richtek,rtmv20";
         reg = <0x34>;
         wakeup-source;
-        interrupts-extend = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>;
+        interrupts-extended = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>;
         enable-gpios = <&gpio26 3 0>;
 
-        strobe-polarity-high;
-        vsync-polarity-high;
+        richtek,strobe-polarity-high;
+        richtek,vsync-polarity-high;
 
         lsw {
                 regulator-name = "rtmv20,lsw";

diff --git a/drivers/regulator/rtmv20-regulator.c b/drivers/regulator/rtmv20-regulator.c
index 1075b10..05fd8e7 100644 (file)
--- a/drivers/regulator/rtmv20-regulator.c
+++ b/drivers/regulator/rtmv20-regulator.c
@@ -166,28 +166,32 @@ static int rtmv20_properties_init(struct rtmv20_priv *priv)
                u32 addr;
                u32 mask;
        } props[] = {
-               { "ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
+               { "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
                        RTMV20_DELAY_MASK },
-               { "ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
+               { "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
                        RTMV20_WIDTH_MASK },
-               { "fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
+               { "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
                        RTMV20_DELAY_MASK },
-               { "fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, RTMV20_WIDTH2_MASK },
-               { "fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
+               { "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3,
+                       RTMV20_WIDTH2_MASK },
+               { "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
                        RTMV20_DELAY_MASK },
-               { "fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, RTMV20_WIDTH2_MASK },
-               { "es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
+               { "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3,
+                       RTMV20_WIDTH2_MASK },
+               { "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
                        RTMV20_WIDTH_MASK },
-               { "es-ld-current-microamp", 3000000, 0, 6000000, 30000, RTMV20_REG_ESLDCTRL1,
-                       RTMV20_LDCURR_MASK },
-               { "lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
+               { "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000,
+                       RTMV20_REG_ESLDCTRL1, RTMV20_LDCURR_MASK },
+               { "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
                        RTMV20_LBPLVL_MASK },
-               { "lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
-               { "strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_STROBEPOL_MASK },
-               { "vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_VSYNPOL_MASK },
-               { "fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
-               { "fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
-               { "es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
+               { "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
+               { "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
+                       RTMV20_STROBEPOL_MASK },
+               { "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
+                       RTMV20_VSYNPOL_MASK },
+               { "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
+               { "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
+               { "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
        };
        int i, ret;